ST STEVAL-IME015V1, User Manual, Page: 7 / 25

Figure 6. STHV64SW timing diagram
DIN
LE_n
CLK
DOUT
CLR
50%
50%
50% 50%
50%
50%
50% 50%
Din
N
Din
63
t
SU
t
WLE
t
H
t
CLE
t
DO
t
WCL
Dout
N
Dout
63
Din
0
Dout
0
50%
Figure 7. STHV64SW digital interface block diagram
Digital interface minimum required signals:
•
DIN – Data In
–
1 for ON-STATE
– 0 for OFF-STATE
• CLK – Clock Signal
–
20 MHz typical freq.
• LE_N – Latch Enable (Active LOW)
–
Allows writing the status in the switch latch to turn the switch on or off
Digital interface optional signals
•
DOUT – Data Out
–
Available for daisy-chain connection of 2 or more STHV64SW devices. Can be left floating when not
used.
• CLR – Clear Signals (Active HIGH)
–
Resets the Latches to 0 (switches OFF), allowing the previous state to be left in the FF, available to be
written again in the Latches through LE_N. To be left to GND when not used.
UM2482
Digital interface
UM2482 - Rev 1
page 7/25