ST STEVAL-ETH001V1, Getting Started

Page: 7 / 40

Figure 8. Digital input/output circuit
+Vbus +Vbus
3v3 3v3
3v3 3v3
+Vbus +Vbus
+Vbus +Vbus
+Vbus +Vbus
16
0H
_I
N
2
16
0H
_I
N
2
16
0H
_I
N
1
16
0H
_I
N
1
CLT03_OUT2 CLT03_OUT2
160H_DIAG1 160H_DIAG1
160H_DIAG2 160H_DIAG2
CLT03_OUT1 CLT03_OUT1
D2
LED RED D2
LED RED
AA
CC
C10
2.2uF
C10
2.2uF
C9
10nF
C9
10nF
R1
10k R1
10k
C4
4.7nF
C4
4.7nF
N.M.
N.M.
U2
CLT03-2Q3
U2
CLT03-2Q3
PD2 PD2
11
INA2 INA2
33
INATTL2 INATTL2
22
INB2 INB2
44
OUTN1 OUTN1
55
INATTL1 INATTL1
66
INA1 INA1
77
INB1 INB1
88
T
P
1
T
P
1
99
V
B
U
F
1
V
B
U
F
1
1
0
1
0
OUTP1 OUTP1
11 11
PD1 PD1
12 12
OUTN2 OUTN2
13 13
T
P
2
T
P
2
1
4
1
4
V
B
U
F
2
V
B
U
F
2
1
5
1
5
OUTP2 OUTP2
16 16
OUTN1_T OUTN1_T
TAB1 TAB1
OUTN2_T OUTN2_T
TAB2 TAB2
U3
IPS160H
U3
IPS160H
Vcc1 Vcc1
11
IN IN
22
DIAG DIAG
33
CoD CoD
44
NC1 NC1
55
NC2 NC2
66
GND GND
77
OUT1 OUT1
88
OUT2 OUT2
99
OUT3 OUT3
10 10
OUT4 OUT4
11 11
Vcc2 Vcc2
12 12
V
cc
_
T
A
B
V
cc
_
T
A
B
1
3
1
3
J14
Con2
J14
Con2
11
22
R4
10k R4
10k
C12
100nF
C12
100nF
U1
IPS160H
U1
IPS160H
Vcc1 Vcc1
11
IN IN
22
DIAG DIAG
33
CoD CoD
44
NC1 NC1
55
NC2 NC2
66
GND GND
77
OUT1 OUT1
88
OUT2 OUT2
99
OUT3 OUT3
10 10
OUT4 OUT4
11 11
Vcc2 Vcc2
12 12
V
cc
_
T
A
B
V
cc
_
T
A
B
1
3
1
3
R2
0 R2
0
J2
CON3
J2
CON3
11
22
33
C6
10nF C6
10nF
C3
10nF C3
10nF
C8
4.7nF
C8
4.7nF
N.M.
N.M.
C5
100nF
C5
100nF
C1
2.2uF
C1
2.2uF
C11
0.1uF
C11
0.1uF
C7
10nF C7
10nF
D1
LED RED D1
LED RED
AA
CC
R5
0
R5
0
C2
0.1uF
C2
0.1uF
PD2 PD2
PD2 PD2
Actuator connector
2.5 Power management
The power stage circuit consists of an input stage with 48 V max. operating voltage and 60 V max. overvoltage,
embedding two 330µF/100V electrolytic bulk capacitors with Transil protection, and two DC-DC converters in buck
configuration to regulate the 3.8 V and the 15 V.
The 3.8 V regulates the 3.3 V with max. output current of 1 A for the digital circuit ( i.e. microcontroller,
ST3485EI
transceiver, NETX90); the 15 V is used, instead, for the STDRIVE101 digital supply and to regulate the 5 V with
200 mA output current supplying the encoder.
Both regulation circuits have been built using the
L7987L switching regulator in TSSOP package. Two linear
regulators have been inserted in series into the switching regulator to improve the ripple on the regulated low
voltage reference (3.3 V and 5 V): in particular, the
LD39150DT33-R low drop has been used for the 3.3 V and
the L7805CD2T-TR linear regulator has been used for the 5 V.
Figure 9. DC-DC converter - V
BUS
to 3.8 V regulation
560.9 kHz
3v8
+Vbus
3v8
C107
47uF
C102
0.1uF
D17
STPS2L60A
R128
0
C104
1 uF C105
1 uF
TP1
5001
C103
4.7uF
R133
68k
C98
1uF
R130
L5
10uH
1 2
C100
100pF
C99
820pF
R131
40.2k L7987L
U14
VBIAS
1
VIN
2
VIN_2
3
VCC
4
EN
5
SS
6
SYNCH
7
COMP
8
FB
9
FSW
10
ILIM
11
PGOOD
12
LX
13
LX_2
14
BOOT
15
GND
16
EP
17
C106
22nF
R129
680R
R132
33k
R134
18k
11
10
7
6
SS
5
4
3
2
U14
C100
2 1
L5
10uH
5.6k
C98
C103
TP1
C105 C104
C101
22nF
R128
0
+Vbus
3v8
UM2807
Power management
UM2807 - Rev 1
page 7/40