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ST7LITEUS2, ST7LITEUS5
Power saving modes
53/136
Figure 23.
Halt timing overview
1.
A reset pulse of at least 42µs must be applied when exiting from Halt mode.
Figure 24.
Halt mode flowchart
1.
WDGHALT is an option bit. See option byte section for more details.
2.
Peripheral clocked with an external clock source can still be active.
3.
Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
for more details.
4.
Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
5.
The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.
Halt
Run
Run
64 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
[
Active-halt disabled
]
HALT
INSTRUCTION
RESET
INTERRUPT
3)
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS
2)
I BIT
OFF
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
I BIT
ON
OFF
X
4)
ON
CPU
OSCILLATOR
PERIPHERALS
I BITS
ON
ON
X
4)
ON
64 CPU CLOCK CYCLE
DELAY
5)
WATCHDOG
ENABLE
DISABLE
WDGHALT
1)
0
WATCHDOG
RESET
1
(Active-halt disabled)
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