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ST

 

                                                                     

ST7735R

 

262K Color Single-Chip TFT Controller/Driver

 

V0.2 

1 

2009-8-5 

 
1 

Introduction 

The ST7735R is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 396 source line and 162 
gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial 
Peripheral Interface (SPI), 8-bit/9-bit/16-bit/18-bit parallel interface. Display data can be stored in the on-chip display data 
RAM of 132 x 162 x 18 bits. It can perform display data RAM read/write operation with no external operation clock to 
minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, 
it is possible to make a display system with fewer components. 

2 

Features 

Single chip TFT-LCD Controller/Driver with RAM 
On-chip Display Data RAM (i.e. Frame Memory) 
132 (H) x RGB x 162 (V) bits 
 
LCD Driver Output Circuits: 
Source Outputs: 132 RGB channels 
Gate Outputs: 162 channels 
Common electrode output 
 
Display Colors (Color Mode) 
Full Color: 262K, RGB=(666) max., Idle Mode OFF 
Color Reduce: 8-color, RGB=(111), Idle Mode ON 
 
Programmable Pixel Color Format (Color Depth) for 
Various Display Data input Format 
12-bit/pixel: RGB=(444) using the 384k-bit frame memory 
and LUT 
16-bit/pixel: RGB=(565) using the 384k-bit frame memory 
and LUT 
18-bit/pixel: RGB=(666) using the 384k-bit frame memory 
and LUT 
 
Various Interfaces 
Parallel 8080-series MCU Interface   
(8-bit, 9-bit, 16-bit & 18-bit) 
Parallel 6800-series MCU Interface   
(8-bit, 9-bit, 16-bit & 18-bit) 
3-line serial interface 
4-line serial interface 
 
Display Features 
Support both normal-black & normal-white LC 
Software programmable color depth mode 

Built-in Circuits 
DC/DC converter 
Adjustable VCOM generation 
Non-volatile (NV) memory to store initial register setting 
Oscillator for display clock generation 
Factory default value (module ID, module version, etc) are 
stored in NV memory 
Timing controller 
 
Built-in NV Memory for LCD Initial Register Setting 
7-bits for ID2 
8-bits for ID3 
7-bits for VCOM adjustment 
 
Wide Supply Voltage Range 
I/O Voltage (VDDI to DGND):

 

1.65V~3.7V (VDDI 

≤

 VDD) 

Analog Voltage (VDD to AGND): 2.3V~4.8V 
 
On-Chip Power System 
Source Voltage (GVDD to AGND): 3.0V~4.5V 
VCOM level (VCOM to AGND): -0.4V to -2.0V

 

Gate driver HIGH level (VGH to AGND): +10.0V to +15V 
Gate driver LOW level (VGL to AGND): -13V to -7.5V 
 
Operating Temperature: -30°C to +85°C 
 

 
 
 
 
 

ST7735R 

Parallel Interface: 8080,6800(8-bit/9-bit/16-bit/18-bit) 
Serial Interface: 3-line, 4-line 

 

Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. 

Summary of Contents for ST7735R

Page 1: ...ut Format 12 bit pixel RGB 444 using the 384k bit frame memory and LUT 16 bit pixel RGB 565 using the 384k bit frame memory and LUT 18 bit pixel RGB 666 using the 384k bit frame memory and LUT Various Interfaces Parallel 8080 series MCU Interface 8 bit 9 bit 16 bit 18 bit Parallel 6800 series MCU Interface 8 bit 9 bit 16 bit 18 bit 3 line serial interface 4 line serial interface Display Features S...

Page 2: ...t Bump Dimension C K H A L J Boundary Include scribe Lane Item Symbol Size Bump pitch A 16 um Bump width C 16 um Bump height H 98 um Bump gap1 Vertical J 19 um Bump gap2 Horizontal K 16 um Bump area C x H 1568 um2 Chip Boundary include scribe Lane L 59 um ...

Page 3: ...lude scribe Lane Item Symbol Size Bump pitch 1 A1 67 um Bump pitch 2 A2 50 um Bump width 1 C1 33 um Bump width 2 C2 38 um Bump height H 88 um Bump gap K 22 um Bump gap1 K1 17 um Bump gap2 K2 34 um Bump area 1 C1 X H 2904 um2 Bump area 2 C2 X H 3344 um2 Chip Boundary include scribe Lane L 59 um ...

Page 4: ...ST7735R V0 2 4 2009 08 05 3 3 Alignment Mark Dimension 80 80 20 15 15 15 15 10 5 20 15 15 15 15 80 80 20 15 15 15 15 10 5 20 15 15 15 15 ...

Page 5: ... 2009 08 05 3 4 Chip Information Chip size um x um 10080 x 670 PAD coordinate pad center Coordinate origin chip center Chip thickness um 300 TYP Bump height um 15 TYP Bump hardness HV 75 TYP No 1 No 185 No 186 No 759 ...

Page 6: ...1 1030 231 123 AVDD 1650 231 24 DGNDO 3600 231 74 D 10 970 231 124 AVDD 1700 231 25 Dummy 3550 231 75 D 9 910 231 125 Dummy 1750 231 26 VDDIO 3500 231 76 D 8 850 231 126 Dummy 1800 231 27 Dummy 3450 231 77 D 1 790 231 127 Dummy 1850 231 28 DGNDO 3400 231 78 D 3 730 231 128 Dummy 1900 231 29 Dummy 3350 231 79 D 5 670 231 129 Dummy 1950 231 30 VDDIO 3300 231 80 D 7 610 231 130 Dummy 2000 231 31 LCM ...

Page 7: ... 223 G92 4180 227 273 S396 3380 227 174 Dummy 4200 231 224 G90 4164 110 274 S395 3364 110 175 Dummy 4250 231 225 G88 4148 227 275 S394 3348 227 176 Dummy 4300 231 226 G86 4132 110 276 S393 3332 110 177 Dummy 4350 231 227 G84 4116 227 277 S392 3316 227 178 Dummy 4400 231 228 G82 4100 110 278 S391 3300 110 179 Dummy 4450 231 229 G80 4084 227 279 S390 3284 227 180 Dummy 4500 231 230 G78 4068 110 280 ...

Page 8: ...580 227 373 S296 1780 227 423 S246 980 227 324 S345 2564 110 374 S295 1764 110 424 S245 964 110 325 S344 2548 227 375 S294 1748 227 425 S244 948 227 326 S343 2532 110 376 S293 1732 110 426 S243 932 110 327 S342 2516 227 377 S292 1716 227 427 S242 916 227 328 S341 2500 110 378 S291 1700 110 428 S241 900 110 329 S340 2484 227 379 S290 1684 227 429 S240 884 227 330 S339 2468 110 380 S289 1668 110 430...

Page 9: ...523 S150 996 110 573 S100 1796 110 474 Dummy 212 227 524 S149 1012 227 574 S99 1812 227 475 S198 228 110 525 S148 1028 110 575 S98 1828 110 476 S197 244 227 526 S147 1044 227 576 S97 1844 227 477 S196 260 110 527 S146 1060 110 577 S96 1860 110 478 S195 276 227 528 S145 1076 227 578 S95 1876 227 479 S194 292 110 529 S144 1092 110 579 S94 1892 110 480 S193 308 227 530 S143 1108 227 580 S93 1908 227 ...

Page 10: ...110 723 G93 4196 110 624 S49 2612 227 674 Dummy 3412 227 724 G95 4212 227 625 S48 2628 110 675 Dummy 3428 110 725 G97 4228 110 626 S47 2644 227 676 Dummy 3444 227 726 G99 4244 227 627 S46 2660 110 677 G1 3460 110 727 G101 4260 110 628 S45 2676 227 678 G3 3476 227 728 G103 4276 227 629 S44 2692 110 679 G5 3492 110 729 G105 4292 110 630 S43 2708 227 680 G7 3508 227 730 G107 4308 227 631 S42 2724 110...

Page 11: ... 05 No PAD Name X Y 751 G149 4644 110 752 G151 4660 227 753 G153 4676 110 754 G155 4692 227 755 G157 4708 110 756 G159 4724 227 757 G161 4740 110 758 Dummy 4756 227 759 Dummy 4772 110 ALIGNMENT_R 4841 220 ALIGNMENT_L 4841 220 ...

Page 12: ...e Display Ram 132x 162x18 bits Voltage Reference Gamma Circuit Gamma Table Display control 162 Gate Buffer Level Shifter Gate Decoder Vcom generator OSC Booster1 2 4 Instruction Register NVM MCU IF SDA LCM SRGB GS WRX R WX RDX E CSX DC X SCL IM 2 0 EXTC SMX SMY D 17 0 AVDD VDDI VDD GVDD VCOM GVCL AVCL VGH VGL TESEL ...

Page 13: ... IM2 0 Serial interface DGND VDDI IM1 IM0 I MCU parallel interface type selection If not used please fix this pin at VDDI or DGND level IM1 IM0 Parallel interface 0 0 MCU 8 bit parallel 0 1 MCU 16 bit parallel 1 0 MCU 9 bit parallel 1 1 MCU 18 bit parallel DGND VDDI SPI4W I SPI4W 0 3 line SPI enable SPI4W 1 4 line SPI enable If not used please fix this pin at DGND level DGND VDDI RESX I This signa...

Page 14: ... interface D 17 1 are not used and should be fixed at VDDI or DGND level MCU TE O Tearing effect output pin to synchronies MCU to frame rate activated by S W command If not used please open this pin MCU OSC O Monitoring pin of internal oscillator clock and is turned ON OFF by S W command When this pin is inactive function OFF this pin is DGND level If not used please open this pin Note1 When in pa...

Page 15: ...setting SRGB RGB arrangement 0 S1 S2 S3 filter order R G B 1 S1 S2 S3 filter order B G R VDDI DGND SMX I Module source output direction H W selection pin SMX Scanning direction of source output GM 00 GM 11 0 S1 S396 S7 S390 1 S396 S1 S390 S7 VDDI DGND SMY I Module Gate output direction H W selection pin SMY Scanning direction of gate output GM 00 GM 11 0 G1 G162 G2 G161 1 G162 G1 G161 G2 VDDI DGND...

Page 16: ... pin for generating GVCL Connect a capacitor for stabilization Capacitor VGH O Power output pin for gate driver VGL O Power output Negative pin for gate driver GVDD O A power output of grayscale voltage generator When internal GVDD generator is not used connect an external power supply AVDD 0 5V to this pin GVCL O A power output Negative of grayscale voltage generator When internal GVCL generator ...

Page 17: ... used Please connect these pins to DGND DGND TESTOP 8 TESTOP 7 TESTOP 6 TESTOP 5 TESTOP 4 TESTOP 3 TESTOP 2 TESTOP 1 O These test pins for Driver vender test used Please open these pins Open Dummy These pins are dummy have no function inside Can allow signal traces pass through these pads on TFT glass Please open these pins Open ...

Page 18: ... 0 V Logic input voltage range VIN 0 3 VDDI 0 3 V Logic output voltage range VO 0 3 VDDI 0 3 V Operating temperature range TOPR 30 85 Storage temperature range TSTG 40 125 Note If one of the above items is exceeded its maximum limitation momentarily the quality of the product may be degraded Absolute maximum limitation therefore specify the values exceeding which the product may be physically dama...

Page 19: ... Logic high output voltage VOH IOH 1 0mA 0 8VDDI VDDI V Note 1 Logic low output voltage VOL IOL 1 0mA VSS 0 2VDDI V Note 1 Logic high input current IIH VIN VDDI 1 uA Note 1 Logic low input current IIL VIN VSS 1 uA Note 1 Input leakage current IIL IOH 1 0mA 0 1 0 1 uA Note 1 VCOM voltage VCOM amplitude VCOM 2 0 425 V Source driver Source output range Vsout 0 1 GVDD V Gamma reference voltage GVDD 3 ...

Page 20: ...ge IDDI mA IDD mA IDDI mA IDD mA Note 1 TBD TBD TBD TBD Normal mode Note 2 TBD TBD TBD TBD Note 1 TBD TBD TBD TBD Partial Idle mode 40 lines Note 2 TBD TBD TBD TBD Sleep in mode N A TBD TBD TBD TBD Notes 1 All pixels black 2 All pixels white 3 The Current Consumption is DC characteristics of ST7735R 4 Typical VDDI 1 8V VDD 2 75V Maximum VDDI 1 65 to 3 7V VDD 2 3 to 4 8V ...

Page 21: ...t setup time Read FM 355 ns TCSF Chip select wait time Write Read 10 ns CSX TCSH Chip select hold time 10 ns TWC Write cycle 66 ns TWRH Control pulse H duration 15 ns WRX TWRL Control pulse L duration 15 ns TRC Read cycle ID 160 ns TRDH Control pulse H duration ID 90 ns RDX ID TRDL Control pulse L duration ID 45 ns When read ID data TRCFM Read cycle FM 450 ns TRDHFM Control pulse H duration FM 90 ...

Page 22: ...and output signal Figure 8 1 3 Chip selection CSX timing Figure 8 1 4 Write to read and read to write timing Note The rising time and falling time Tr Tf of input signal are specified at 15 ns or less Logic high and low levels are specified as 30 and 70 of VDDI for Input signals ...

Page 23: ...X TCSH Chip select hold time 10 ns TWC Write cycle 66 ns TWRH Control pulse H duration 15 ns WRX TWRL Control pulse L duration 15 ns TRC Read cycle ID 160 ns TRDH Control pulse H duration ID 90 ns RDX ID TRDL Control pulse L duration ID 45 ns When read ID data TRCFM Read cycle FM 450 ns TRDHFM Control pulse H duration FM 90 ns RDX FM TRDLFM Control pulse L duration FM 355 ns When read from frame m...

Page 24: ...lect hold time read 65 ns CSX TCHW Chip select H pulse width 40 ns TSCYCW Serial clock cycle Write 66 ns TSHW SCL H pulse width Write 15 ns TSLW SCL L pulse width Write 15 ns TSCYCR Serial clock cycle Read 150 ns TSHR SCL H pulse width Read 60 ns SCL TSLR SCL L pulse width Read 60 ns TSDS Data setup time 10 ns TSDH Data hold time 10 ns TACC Access time 10 50 ns SDA DIN DOUT TOH Output disable time...

Page 25: ...lse width Write 15 ns TSLW SCL L pulse width Write 15 ns write command data ram TSCYCR Serial clock cycle Read 150 ns TSHR SCL H pulse width Read 60 ns SCL TSLR SCL L pulse width Read 60 ns read command data ram TDCS D CX setup time 10 ns D CX TDCH D CX hold time 10 ns TSDS Data setup time 10 ns TSDH Data hold time 10 ns TACC Access time 10 50 ns SDA DIN DOUT TOH Output disable time 15 50 ns For m...

Page 26: ...6800 MCU 9 bit parallel E strobe 9 bit read data and 8 bit read parameter 1 1 1 1 6800 MCU 18 bit parallel E strobe 18 bit read data and 8 bit read parameter Table 9 1 1 Selection of MCU interface P68 IM2 IM1 IM0 Interface RDX WRX D CX Read back selection 0 3 line serial interface Note1 Note1 SCL D 17 1 unused D0 SDA 0 1 0 0 8080 8 bit parallel RDX WRX D CX D 17 8 unused D7 D0 8 bit data 0 1 0 1 8...

Page 27: ...owing table IM2 IM1 IM0 Interface D CX RDX WRX Read back selection 0 1 Write 8 bit command D7 to D0 1 1 Write 8 bit display data or 8 bit parameter D7 to D0 1 1 Read 8 bit display data D7 to D0 1 0 0 8 bit parallel 1 1 Read 8 bit parameter or status D7 to D0 0 1 Write 8 bit command D7 to D0 1 1 Write 16 bit display data or 8 bit parameter D15 to D0 1 1 Read 16 bit display data D15 to D0 1 0 1 16 b...

Page 28: ...0 lines when there is a falling edge of the WRX The display writes D 17 0 lines when there is a rising edge of WRX The host stops to control D 17 0 lines Figure 9 2 1 8080 series WRX protocol Note WRX is an unsynchronized signal It can be stopped CMD CMD PA1 CMD PA1 PAN 2 PAN 1 S P CMD CMD PA1 CMD PA1 PAN 2 PAN 1 S P CMD CMD PA1 CMD PA1 PAN 2 PAN 1 S P D 17 0 RESX CSX D CX RDX WRX D 17 0 Host D 17...

Page 29: ...s RDX protocol Note RDX is an unsynchronized signal It can be stopped CMD DM PA CMD DM data Data Data S P CMD DM PA CMD DM data Data Data S P D 17 0 RESX CSX D CX RDX WRX D 17 0 Host D 17 0 Host to LCD Driver D 17 0 LCD to Host 1 Hi Z Read parameter Read display data CMD write command code PA parameter or display data Signals on D 17 0 D CX R WX E pins during CSX 1 are ignored DM PA1 DM data PAN 2...

Page 30: ... data or 8 bit parameter D7 to D0 1 1 Read 8 bit Display data D7 to D0 1 1 0 0 8 bit Parallel 1 1 Read 8 bit parameter or status D7 to D0 0 0 Write 8 bit command D7 to D0 1 0 Write 16 bit display data or 8 bit parameter D15 to D0 1 1 Read 16 bit Display data D15 to D0 1 1 0 1 16 bit Parallel 1 1 Read 8 bit parameter or status D7 to D0 0 0 Write 8 bit command D7 to D0 1 0 Write 9 bit display data o...

Page 31: ...ST7735R V0 2 31 2009 08 05 Figure 9 3 2 6800 series parallel bus protocol write to register or display RAM ...

Page 32: ...rom LCD driver via interface The driver sends data D 17 0 to the host when there is a rising edge of E and the host reads data when there is a falling edge of E Figure 9 3 3 6800 series read protocol Note E is an unsynchronized signal It can be stopped Figure 9 3 4 6800 series parallel bus protocol read data form register or display RAM ...

Page 33: ... In 4 lines serial interface data packet contains just transmission byte and control bit D CX is transferred by the D CX pin If D CX is low the transmission byte is interpreted as a command byte If D CX is high the transmission byte is stored in the display data RAM memory write command or command register as parameter Any instruction can be sent in any order to the driver The MSB is transmitted f...

Page 34: ...function the micro controller first has to send a command read ID or register command and then the following byte is transmitted in the opposite direction After that CSX is required to go to high before a new command is send see the below figure The driver samples the SDA input data at rising edge of SCL but shifts SDA output data at the falling edge of SCL Thus the micro controller is supported t...

Page 35: ...otocol 3 line serial protocol for RDID1 RDID2 RDID3 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh command 8 bit read 3 line serial protocol for RDDID command 24 bit read 3 line Serial Protocol for RDDST command 32 bit read Figure 9 4 5 3 line serial interface read protocol ...

Page 36: ... 4 line serial protocol for RDID1 RDID2 RDID3 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh command 8 bit read 4 line serial protocol for RDDID command 24 bit read 4 line Serial Protocol for RDDST command 32 bit read Host Driver Figure 9 4 6 4 line serial interface read protocol ...

Page 37: ...y CSX pulse while transferring a command or frame memory data or multiple parameter command data before Bit D0 of the byte has been completed then driver will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re transmitted when the chip select line CSX is next activated See the following example Figure 9 5 2 Serial bus protocol write mode in...

Page 38: ... parameter commands are being sent and a break occurs by the other command before the last one is sent then the parameters that were successfully sent are stored and the other parameter of that command remains previous value Figure 9 5 4 Write interrupts recovery both serial and parallel Interface ...

Page 39: ... from the point where it was paused If the chip select Line is released after a whole byte of a command has been completed then the display module will receive either the command s parameters if appropriate or a new command when the chip select line is next enabled as shown below This applies to the following 4 conditions 1 Command Pause Command 2 Command Pause Parameter 3 Parameter Pause Command ...

Page 40: ...successive frame writes each time the frame memory is filled the frame memory pointer is reset to the start point and the next frame is written 9 7 2 Method 2 The image data is sent and at the end of each frame memory download a command is sent to stop frame memory write Then start memory write command is sent and a new frame is downloaded Note 1 These apply to all data transfer Color modes on bot...

Page 41: ...1 Bit 0 B1 Bit 0 G2 Bit 0 R3 Bit 0 0 G1 Bit 3 R2 Bit 3 B2 Bit 3 G3 Bit 3 1 G1 Bit 2 R2 Bit 2 B2 Bit 2 G3 Bit 2 1 G1 Bit 1 R2 Bit 1 B2 Bit 1 G3 Bit 1 0 G1 Bit 0 R2 Bit 0 B2 Bit 0 G3 Bit 0 0 8080 series control pins RESX IM 2 0 CSX D CX 1 1 1 1 100 WRX RDX 1 D7 D6 D5 D4 D3 D2 D1 D0 Pixel n Pixel n 1 Look up table for 4096 color data mapping 12 bits to 18 bits 12 bits 12 bits R1 G1 B1 R2 G2 B2 R3 G3 ...

Page 42: ... D3 D2 D1 D0 Pixel n Pixel n 1 Look up table for 65k color data mapping 16 bits to 18 bits 16 bits 16 bits R1 G1 B1 R2 G2 B2 R3 G3 B3 18 bits Frame memory R2 Bit 4 G2 Bit 2 R2 Bit 3 G2 Bit 1 R2 Bit 2 G2 Bit 0 R2 Bit 1 B2 Bit 4 R2 Bit 0 B2 Bit 3 G2 Bit 5 B2 Bit 2 G2 Bit 4 B2 Bit 1 G2 Bit 3 B2 Bit 0 Note 1 The data order is as follows MSB D7 LSB D0 and picture data is MSB Bit 5 LSB Bit 0 for Green a...

Page 43: ...2 D1 D0 Pixel n Pixel n 1 18 bits 18 bits R1 G1 B1 R2 G2 B2 R3 G3 B3 Frame memory G1 Bit 4 G1 Bit 3 G1 Bit 2 G1 Bit 1 G1 Bit 0 G1 Bit 5 B1 Bit 4 B1 Bit 3 B1 Bit 2 B1 Bit 1 B1 Bit 0 B1 Bit 5 R2 Bit 4 R2 Bit 3 R2 Bit 2 R2 Bit 1 R2 Bit 0 R2 Bit 5 Note 1 The data order is as follows MSB D7 LSB D0 and picture data is MSB Bit 5 LSB Bit 0 for Red Green and Blue data Note 2 3 times transfer is used to tra...

Page 44: ... B3 18 bits Frame memory R1 Bit 3 0 R1 Bit 2 0 R1 Bit 1 1 R1 Bit 0 0 1 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 B1 Bit 3 B1 Bit 2 B1 Bit 1 B1 Bit 0 G2 Bit 3 G2 Bit 2 G2 Bit 1 G2 Bit 0 R2 Bit 3 R2 Bit 2 R2 Bit 1 R2 Bit 0 B2 Bit 3 B2 Bit 2 B2 Bit 1 B2 Bit 0 G3 Bit 3 G3 Bit 2 G3 Bit 1 G3 Bit 0 R3 Bit 3 R3 Bit 2 R3 Bit 1 R3 Bit 0 B3 Bit 3 B3 Bit 2 B3 Bit 1 B3 Bit 0 G4 Bit 3 G4 Bit 2 G4 Bit 1 G4 Bit 0 R4 Bit 3 R4...

Page 45: ...it 2 B2 Bit 1 B2 Bit 0 G3 Bit 3 G3 Bit 2 G3 Bit 1 G3 Bit 0 R3 Bit 3 R3 Bit 2 R3 Bit 1 R3 Bit 0 B3 Bit 3 B3 Bit 2 B3 Bit 1 B3 Bit 0 G4 Bit 3 G4 Bit 2 G4 Bit 1 G4 Bit 0 R4 Bit 3 R4 Bit 2 R4 Bit 1 R4 Bit 0 B4 Bit 3 B4 Bit 2 B4 Bit 1 B4 Bit 0 Pixel n 2 Pixel n 3 Look up table for 65k color data mapping 16 bits to 18 bits B1 Bit 4 B2 Bit 4 B3 Bit 4 B4 Bit 4 R1 Bit 4 R2 Bit 4 R3 Bit 4 R4 Bit 4 G1 Bit 5 ...

Page 46: ... Bit 0 B2 Bit 3 B2 Bit 2 B2 Bit 1 B2 Bit 0 B1 Bit 4 B2 Bit 4 R1 Bit 4 G1 Bit 3 G1 Bit 2 G1 Bit 1 G1 Bit 0 G3 Bit 3 G3 Bit 2 G3 Bit 1 G3 Bit 0 G1 Bit 5 G1 Bit 4 G3 Bit 5 G3 Bit 4 R1 Bit 5 B1 Bit 5 B2 Bit 5 R2 Bit 3 R2 Bit 2 R2 Bit 1 R2 Bit 0 R2 Bit 4 R2 Bit 5 G2 Bit 3 G2 Bit 2 G2 Bit 1 G2 Bit 0 G2 Bit 5 G2 Bit 4 R3 Bit 3 R3 Bit 2 R3 Bit 1 R3 Bit 0 R3 Bit 4 R3 Bit 5 Note 1 The data order is as follo...

Page 47: ...DX 1 D7 D6 D5 D4 D3 D2 D1 D0 Pixel n Pixel n 1 18 bits 18 bits R1 G1 B1 R2 G2 B2 R3 G3 B3 Frame memory G1 Bit 4 G1 Bit 3 G1 Bit 2 G1 Bit 1 G1 Bit 0 B1 Bit 4 B1 Bit 3 B1 Bit 2 B1 Bit 1 B1 Bit 0 B1 Bit 5 R2 Bit 4 R2 Bit 3 R2 Bit 2 R2 Bit 1 R2 Bit 0 R2 Bit 5 G1 Bit 5 D8 G2 Bit 4 G2 Bit 3 G2 Bit 5 B2 Bit 4 B2 Bit 3 B2 Bit 2 B2 Bit 1 B2 Bit 0 B2 Bit 5 G2 Bit 2 G2 Bit 1 G2 Bit 0 Note 1 The data order is...

Page 48: ...G3 B3 18 bits Frame memory R1 Bit 3 0 R1 Bit 2 0 R1 Bit 1 1 R1 Bit 0 0 1 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 B1 Bit 3 B1 Bit 2 B1 Bit 1 B1 Bit 0 G2 Bit 3 G2 Bit 2 G2 Bit 1 G2 Bit 0 R2 Bit 3 R2 Bit 2 R2 Bit 1 R2 Bit 0 B2 Bit 3 B2 Bit 2 B2 Bit 1 B2 Bit 0 G3 Bit 3 G3 Bit 2 G3 Bit 1 G3 Bit 0 R3 Bit 3 R3 Bit 2 R3 Bit 1 R3 Bit 0 B3 Bit 3 B3 Bit 2 B3 Bit 1 B3 Bit 0 G4 Bit 3 G4 Bit 2 G4 Bit 1 G4 Bit 0 R4 Bit 3 ...

Page 49: ...2 Bit 0 B2 Bit 3 B2 Bit 2 B2 Bit 1 B2 Bit 0 G3 Bit 3 G3 Bit 2 G3 Bit 1 G3 Bit 0 R3 Bit 3 R3 Bit 2 R3 Bit 1 R3 Bit 0 B3 Bit 3 B3 Bit 2 B3 Bit 1 B3 Bit 0 G4 Bit 3 G4 Bit 2 G4 Bit 1 G4 Bit 0 R4 Bit 3 R4 Bit 2 R4 Bit 1 R4 Bit 0 B4 Bit 3 B4 Bit 2 B4 Bit 1 B4 Bit 0 Pixel n 2 Pixel n 3 Look up table for 65k color data mapping 16 bits to 18 bits D17 D16 R1 Bit 4 R2 Bit 4 R3 Bit 4 R4 Bit 4 G1 Bit 5 G1 Bit ...

Page 50: ...2 Bit 0 B2 Bit 3 B2 Bit 2 B2 Bit 1 B2 Bit 0 G3 Bit 3 G3 Bit 2 G3 Bit 1 G3 Bit 0 R3 Bit 3 R3 Bit 2 R3 Bit 1 R3 Bit 0 B3 Bit 3 B3 Bit 2 B3 Bit 1 B3 Bit 0 G4 Bit 3 G4 Bit 2 G4 Bit 1 G4 Bit 0 R4 Bit 3 R4 Bit 2 R4 Bit 1 R4 Bit 0 B4 Bit 3 B4 Bit 2 B4 Bit 1 B4 Bit 0 Pixel n 2 Pixel n 3 D17 D16 R1 Bit 4 R2 Bit 4 R3 Bit 4 R4 Bit 4 G1 Bit 5 G1 Bit 4 G2 Bit 5 G2 Bit 4 G3 Bit 5 G3 Bit 4 G4 Bit 5 G4 Bit 4 B1 B...

Page 51: ...CM listed below 4k colors RGB 4 4 4 bit input 65k colors RGB 5 6 5 bit input 262k colors RGB 6 6 6 bit input 9 8 16 Write data for 12 bit pixel RGB 4 4 4 bit input 4K Colors 3AH 03h Note 1 Pixel data with the 12 bit color depth information Note 2 The most significant bits are Rx3 Gx3 and Bx3 Note 3 The least significant bits are Rx0 Gx0 and Bx0 ...

Page 52: ...7 Write data for 16 bit pixel RGB 5 6 5 bit input 65K Colors 3AH 05h Note 1 Pixel data with the 16 bit color depth information Note 2 The most significant bits are Rx4 Gx5 and Bx4 Note 3 The least significant bits are Rx0 Gx0 and Bx0 ...

Page 53: ...8 Write data for 18 bit pixel RGB 6 6 6 bit input 262K Colors 3AH 06h Note 1 Pixel data with the 18 bit color depth information Note 2 The most significant bits are Rx5 Gx5 and Bx5 Note 3 The least significant bits are Rx0 Gx0 and Bx0 ...

Page 54: ...CM listed below 4k colors RGB 4 4 4 bit input 65k colors RGB 5 6 5 bit input 262k colors RGB 6 6 6 bit input 9 8 20 Write data for 12 bit pixel RGB 4 4 4 bit input 4K Colors 3AH 03h Note 1 pixel data with the 12 bit color depth information Note 2 The most significant bits are Rx3 Gx3 and Bx3 Note 3 The least significant bits are Rx0 Gx0 and Bx0 ...

Page 55: ...mation Note 2 The most significant bits are Rx4 Gx5 and Bx4 Note 3 The least significant bits are Rx0 Gx0 and Bx0 9 8 22 Write data for 18 bit pixel RGB 6 6 6 bit input 262K Colors 3AH 06h Note 1 pixel data with the 18 bit color depth information Note 2 The most significant bits are Rx5 Gx5 and Bx5 Note 3 The least significant bits are Rx0 Gx0 and Bx0 ...

Page 56: ...raphic type static RAM This 384 912 bit memory allows storing on chip a 132xRGBx162 image with an 18 bpp resolution 262K color There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory Figure 9 9 1Display data RAM organization ...

Page 57: ...153 6 156 154 5 154 5 157 155 4 155 4 158 156 3 156 3 159 157 2 157 2 160 158 1 158 1 161 159 0 159 0 MX 0 MX 1 Pixel 1 Pixel 2 Pixel 127 Pixel 128 Source Out RGB 0 RGB 1 RGB 0 RGB 1 RGB Order RGB 0 RGB 1 RGB 0 RGB 1 RA SA CA 0 1 126 127 127 126 1 0 Note RA Row Address CA Column Address SA Scan Address MX Mirror X axis Column address direction parameter D6 parameter of MADCTL command MY Mirror Y a...

Page 58: ...158 157 4 157 4 159 158 3 158 3 160 159 2 159 2 161 160 1 160 1 162 161 0 161 0 MX 0 MX 1 Pixel 1 Pixel 2 Pixel 131 Pixel 132 Source Out RGB 0 RGB 1 RGB 0 RGB 1 RGB Order RGB 0 RGB 1 RGB 0 RGB 1 RA SA CA 0 1 130 131 131 130 1 0 Note RA Row Address CA Column Address SA Scan Address MX Mirror X axis Column address direction parameter D6 parameter of MADCTL command MY Mirror Y axis Row address direct...

Page 59: ...an Order 00 01 02 03 0W 0X 0Y 0Z G2 10 11 12 13 1W 1X 1Y 1Z G3 20 21 22 2X 2Y 2Z G4 30 31 32 3X 3Y 3Z 40 41 42 4X 4Y 4Z 50 51 5Y 5Z 60 6Z S0 SZ U0 U1 UY UZ V0 V1 V2 VX VY VZ W0 W1 W2 WX WY WZ X0 X1 X2 XX XY XZ G159 Y0 Y1 Y2 Y3 YW YX YY YZ G160 Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G161 128RGB x 160 LCD Panel 128 Columns 128 Columns 160 Lines Scan Order 00 01 02 03 0W 0X 0Y 0Z G2 10 11 12 13 1W 1X 1Y 1Z G3 20 21...

Page 60: ...2 13 1W 1X 1Y 1Z G2 20 21 22 2X 2Y 2Z G3 30 31 32 3X 3Y 3Z 40 41 42 4X 4Y 4Z 50 51 5Y 5Z 60 6Z S0 SZ U0 U1 UY UZ V 0 V 1 V 2 V X V Y V Z W0 W1 W2 WX WY WZ X0 X1 X2 XX XY XZ G160 Y0 Y1 Y2 Y3 YW YX YY YZ G161 Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G162 132RGB x 162 132RGB x 162 132RGB x 162 132RGB x 162 LCD Panel LCD Panel LCD Panel LCD Panel 132 Columns 00h 01h 81h 83h 00h 00 01 02 03 0W 0X 0Y 0Z 1 01h 10 11 12 1...

Page 61: ...ts to address the next column In horizontal addressing mode V 0 the X address increments after each byte after the last X address X XE X wraps around to XS and Y increments to address the next row After the every last address X XE and Y YE the address pointers wrap around to address X XS and Y YS For flexibility in handling a wide variety of display architectures the commands CASET RASET and MADCT...

Page 62: ... Row Pointer Direct to 127 Physical Column Pointer 1 1 1 Direct to 159 Physical Row Pointer Direct to 127 Physical Column Pointer 9 11 2 When 132RGBx162 GM 00 MV MX MY CASET RASET 0 0 0 Direct to Physical Column Pointer Direct to Physical Row Pointer 0 0 1 Direct to Physical Column Pointer Direct to 161 Physical Row Pointer 0 1 0 Direct to 131 Physical Column Pointer Direct to Physical Row Pointer...

Page 63: ...ters MV MX and MY MADCTL Parameter Display Data Direction MV MX MY Image in the Host MPU Image in the Driver DDRAM Normal 0 0 0 Y Mirror 0 0 1 X Mirror 0 1 0 X Mirror Y Mirror 0 1 1 X Y Exchange 1 0 0 X Y Exchange Y Mirror 1 0 1 X Y Exchange X Mirror 1 1 0 X Y Exchange X Mirror Y Mirror 1 1 1 ...

Page 64: ...deo images 9 12 1 Tearing Effect Line Modes Mode 1 the Tearing Effect Output signal consists of V Blanking Information only tvdh The LCD display is not updated from the Frame Memory tvdl The LCD display is updated from the Frame Memory except Invisible Line see above Mode 2 the Tearing Effect Output signal consists of V Blanking and H Blanking Information there is one V sync and 162 H sync pulses ...

Page 65: ...ly when MADCTL ML 0 and ML 1 The signal s rise and fall times tf tr are stipulated to be equal to or less than 15ns The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect Symbol Parameter min max unit description tvdl Vertical Timing Low Duration 13 ms tvdh Vertical Timing High Duration 1000 µs thdl Horizontal Timing Low Duration 33 µs thdh ...

Page 66: ... read Data write to Frame Memory is now synchronized to the Panel Scan It should be written during the vertical sync pulse of the Tearing Effect Output Line This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image ...

Page 67: ... begins just after Panel Read has commenced i e after one horizontal sync pulse of the Tearing Effect Output Line This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer catches the MPU to Frame memory write position B ...

Page 68: ...re Reset RESX after Host Power On Sequence is complete to ensure correct operation Otherwise function is not guaranteed The power on off sequence is illustrated below Timing when the latter signal rises up to 90 of its typical value e g When VDD comes later this timing is defined at the cross point of 90 of 2 75V not 90 of 2 6V Timing when the latter signal falls up to 90 of its typical value e g ...

Page 69: ...rs 3 Normal Mode On full display Idle Mode On Sleep Out In this mode the full display area is used but with 8 colors 4 Partial Mode On Idle Mode On Sleep Out In this mode part of the display is used but with 8 colors 5 Sleep In Mode In this mode the DC DC converter internal oscillator and panel driver circuit are stopped Only the MCU interface and memory works with VDDI power supply Contents of th...

Page 70: ...eep in Partial display mode on Idle mode off Sleep out Partial display mode on Idle mode on Sleep in Partial display mode on Idle mode on SLP IN SLP IN SLP IN SLP IN SLP OUT SLP OUT SLP OUT SLP OUT IDM ON IDM OFF IDM ON IDM OFF PTL ON NOR ON PTL ON NOR ON IDM ON IDM OFF PTL ON NOR ON PTL ON NOR ON IDM ON IDM OFF Power on sequence HW reset SW reset Normal display mode on NOR ON Partial display mode...

Page 71: ...ss YE 009Fh 009Fh 009Fh 159d when MV 0 007Fh 127d when MV 1 Gamma setting GC0 GC0 GC0 RGB for 4k and 65k Color Mode Random values Random values No Change Partial Start Address PSL 0000h 0000h 0000h Partial End Address PEL 009Fh 009Fh 009Fh Tearing On Off Off Off Off Tearing Effect Mode 1 0 Mode1 0 Mode1 0 Mode1 Memory Data Access Control MY MX MV ML RGB 0 0 0 0 0 0 0 0 0 0 No Change Interface Pixe...

Page 72: ...h 00A1h 161d when MV 0 0083h 131d when MV 1 Gamma setting GC0 GC0 GC0 RGB for 4k and 65k Color Mode Random values Random values No Change Partial Start Address PSL 0000h 0000h 0000h Partial End Address PEL 00A1h 00A1h 00A1h Tearing On Off Off Off Off Tearing Effect Mode 1 0 Mode1 0 Mode1 0 Mode1 Memory Data Access Control MY MX MV ML RGB 0 0 0 0 0 0 0 0 0 0 No Change Interface Pixel Color Format 6...

Page 73: ...Z Inactive High Z Inactive Input pins During Power On Process After Power On After Hardware Reset After Software Reset During Power Off Process RESX See 9 14 Input valid Input valid Input valid See 9 14 CSX Input invalid Input valid Input valid Input valid Input invalid D CX Input invalid Input valid Input valid Input valid Input invalid WRX Input invalid Input valid Input valid Input valid Input ...

Page 74: ...regular system reset according to the table below RESX Pulse Action Shorter than 5us Reset Rejected Longer than 9us Reset Between 5us and 9us Reset starts 3 During the Resetting period the display will be blanked The display is entering blanking sequence which maximum time is 120 ms when Reset Starts in Sleep Out mode The display remains the blank state in Sleep In mode and then return to Default ...

Page 75: ...35 R234 R233 R232 R231 R230 24 10111 R245 R244 R243 R242 R241 R240 25 11000 R255 R254 R253 R252 R251 R250 26 11001 R265 R264 R263 R262 R261 R260 27 11010 R275 R274 R273 R272 R271 R270 28 11011 R285 R284 R283 R282 R281 R280 29 11100 R295 R294 R293 R292 R291 R290 30 11101 R305 R304 R303 R302 R301 R300 31 11110 RED R315 R314 R313 R312 R311 R310 32 11111 Look Up Table Input Data Color Look Up Table Ou...

Page 76: ... G491 G490 82 110001 G505 G504 G503 G502 G501 G500 83 110010 G515 G514 G513 G512 G511 G510 84 110011 G525 G524 G523 G522 G521 G520 85 110100 G535 G534 G533 G532 G531 G530 86 110101 G545 G544 G543 G542 G541 G540 87 110110 G555 G554 G553 G552 G551 G550 88 110111 G565 G564 G563 G562 G561 G560 89 111000 G575 G574 G573 G572 G571 G570 90 111001 G585 G584 G583 G582 G581 G580 91 111010 G595 G594 G593 G592...

Page 77: ...B210 118 10101 B225 B224 B223 B222 B221 B220 119 10110 B235 B234 B233 B232 B231 B230 120 10111 B245 B244 B243 B242 B241 B240 121 11000 B255 B254 B253 B252 B251 B250 122 11001 B265 B264 B263 B262 B261 B260 123 11010 B275 B274 B273 B272 B271 B270 124 11011 B285 B284 B283 B282 B281 B280 125 11100 B295 B294 B293 B292 B291 B290 126 11101 B305 B304 B303 B302 B301 B300 127 11110 B315 B314 B313 B312 B311 ...

Page 78: ...2 G041 G040 37 0100 G055 G054 G053 G052 G051 G050 38 0101 G065 G064 G063 G062 G061 G060 39 0110 G075 G074 G073 G072 G071 G070 40 0111 G085 G084 G083 G082 G081 G080 41 1000 G095 G094 G093 G092 G091 G090 42 1001 G105 G104 G103 G102 G101 G100 43 1010 G115 G114 G113 G112 G111 G110 44 1011 G125 G124 G123 G122 G121 G120 45 1100 G135 G134 G133 G132 G131 G130 46 1101 G145 G144 G143 G142 G141 G140 47 1110 ...

Page 79: ... 0 1 0 0 1 09h Read Display Status 1 1 Dummy read 1 1 BSTON MY MX MV ML RGB MH ST24 1 1 ST23 IFPF2 IFPF1 IFPF0 IDMON PTLONSLOUT NORON 1 1 VSSON ST14 INVON ST12 ST11 DISON TEON GCS2 RDDST 10 1 4 1 1 GCS1 GCS0 TEM ST4 ST3 ST2 ST1 ST0 0 1 0 0 0 0 1 0 1 0 0Ah Read Display Power 1 1 Dummy read RDDPM 10 1 5 1 1 BSTONIDMONPTLONSLPOUT NORON DISON 0 1 0 0 0 0 1 0 1 1 0Bh Read Display 1 1 Dummy read RDD MAD...

Page 80: ...XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 X address start 0 XS X 1 1 XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE8 CASET 10 1 19 1 1 XE7 XE6 XE5 XE4 XE3 XE2 XE1 XE0 X address end S XE X 0 1 0 0 1 0 1 0 1 1 2Bh Row address set 1 1 YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS8 1 1 YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 Y address start 0 YS Y 1 1 YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE8 RASET 10 1 20 1 1 YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0...

Page 81: ...2 IFPF1IFPF0 Interface format 0 1 1 1 0 1 1 0 1 0 DAh Read ID1 1 1 Dummy read RDID1 10 1 31 1 1 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 Read parameter 0 1 1 1 0 1 1 0 1 1 DBh Read ID2 1 1 Dummy read RDID2 10 1 32 1 1 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 Read parameter 0 1 1 1 0 1 1 1 0 0 DCh Read ID3 1 1 Dummy read RDID3 10 1 33 1 1 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 Read parameter Don t care...

Page 82: ...2 82 2009 08 05 10 1 1 NOP 00h 00H NOP No Operation Inst Para D CX WRX RDX D17 8 D7 D6 D5 D4 D3 D2 D1 D0 HEX NOP 0 1 0 0 0 0 0 0 0 0 00h Parameter No Parameter Description This command is empty command Don t care ...

Page 83: ...d during Sleep In mode it will be necessary to wait 120msec before sending next command The display module loads all default values to the registers during 120msec If Software Reset is applied during Sleep Out or Display On Mode it will be necessary to wait 120msec before sending next command Flow Chart SWRESET Set Commands to S W Default Value Display whole blank screen Sleep In Mode Command Para...

Page 84: ...ter ID17 to ID10 LCD module s manufacturer ID The 3rd parameter ID26 to ID20 LCD module driver version ID The 4th parameter ID37 to UD30 LCD module driver ID Commands RDID1 2 3 DAh DBh DCh read data correspond to the parameters 2 3 4 of the command 04h respectively Don t care Default Default Value Status ID1 ID2 ID3 Power On Sequence NV Value NV Value S W Reset NV Value NV Value H W Reset NV Value...

Page 85: ... when MADCTL 36h D6 1 MV Row Column Exchange MV 1 Row column exchange when MADCTL 36h D5 1 0 Normal when MADCTL 36h D5 0 ML Scan Address Order ML 0 Decrement LCD refresh Top to Bottom when MADCTL 36h D4 0 1 Increment LCD refresh Bottom to Top when MADCTL 36h D4 1 RGB RGB BGR Order RGB 1 BGR When MADCTL 36h D3 1 0 RGB When MADCTL 36h D3 0 MH Horizontal Order 0 Decrement LCD refresh Left to Right wh...

Page 86: ...EM Tearing effect line mode 0 mode1 1 mode2 ST4 For Future Use 0 ST3 For Future Use 0 ST2 For Future Use 0 ST1 For Future Use 0 ST0 For Future Use 0 Don t care Default Status Default Value ST31 to ST0 ST 31 24 ST 23 16 ST 15 8 ST 7 0 Power On Sequence 0000 0000 0110 0001 0000 0000 0000 0000 S W Reset 0xxx0xx00 0xxx 0001 0000 0000 0000 0000 H W Reset 0000 0000 0110 0001 0000 0000 0000 0000 Flow Cha...

Page 87: ...ribed in the table below Don t care Bit Description Value BSTON Booster Voltage Status 1 Booster on 0 Booster off IDMON Idle Mode On Off 1 Idle Mode On 0 Idle Mode Off PTLON Partial Mode On Off 1 Partial Mode On 0 Partial Mode Off SLPON Sleep In Out 1 Sleep Out 0 Sleep In NORON Display Normal Mode On Off 1 Normal Display 0 Partial Display DISON Display On Off 1 Display On 0 Display Off D1 Not Used...

Page 88: ... to Left When MADCTL B6 1 0 Left to Right When MADCTL B6 0 MY Row Address Order 1 Bottom to Top When MADCTL B7 1 0 Top to Bottom When MADCTL B7 0 MV Row Column Order MV 1 Row column exchange MV 1 0 Normal MV 0 ML Vertical Refresh Order 1 LCD Refresh Bottom to Top 0 LCD Refresh Top to Bottom RGB RGB BGR Order 1 BGR 0 RGB MH Horizontal Refresh Order LCD horizontal refresh direction control 0 LCD hor...

Page 89: ... 2nd parameter 1 1 0 0 0 0 IFPF2 IFPF1 IFPF0 Description This command indicates the current status of the display as described in the table below IFPF 2 0 MCU Interface Color Format 011 12 bit pixel 101 16 bit pixel 110 18 bit pixel 111 No used Others are no define and invalid Don t care Default Status Default Value IFPF 2 0 Power On Sequence 0110 18 bits pixel S W Reset No Change H W Reset 0110 1...

Page 90: ...ommand indicates the current status of the display as described in the table below Don t care Bit Description Value VSSON Reversed 0 D6 Reversed 0 INVON Inversion On Off 1 Inversion is On 0 Inversion is Off D4 All Pixels On 0 Not used D3 All Pixels Off 0 Not used GCS2 GCS1 GCS0 Gamma Curve Selection 000 GC0 001 GC1 010 GC2 011 GC3 100 to 111 Not defined Default Status Default Value D7 to D0 Power ...

Page 91: ...tion This command indicates the current status of the display as described in the table below Don t care Bit Description Value TEON Tearing Effect Line On Off 1 On 0 Off TEM Tearing effect line mode 1 mode2 0 mode1 D5 Not Used 1 On 0 Off D4 Not Used 1 On 0 Off D3 Not Used 1 On 0 Off D2 Not Used 1 On 0 Off D1 Not Used 1 On 0 Off D0 Not Used 1 On 0 Off Default Status Default Value D7 D0 Power On Seq...

Page 92: ...ST7735R V0 2 92 2009 08 05 Flow Chart ...

Page 93: ...en module is already in Sleep In mode Sleep In Mode can only be exit by the Sleep Out Command 11h When IC is in Sleep Out or Display On mode it is necessary to wait 120msec before sending next command because of the stabilization timing for the supply voltages and clock circuits Default Status Default Value Power On Sequence Sleep in mode S W Reset Sleep in mode H W Reset Sleep in mode Flow Chart ...

Page 94: ...sending next command because of the stabilization timing for the supply voltages and clock circuits When IC is in Sleep Out or Display On mode it is necessary to wait 120msec before sending next command due to the download of default value of registers and the execution of self diagnostic function Default Status Default Value Power On Sequence Sleep in mode S W Reset Sleep in mode H W Reset Sleep ...

Page 95: ...0 0 1 0 12h Parameter No Parameter Description This command turns on Partial mode The partial mode window is described by the Partial Area command 30h To leave Partial mode the Normal Display Mode On command 13h should be written Don t care Default Status Default Value Power On Sequence Normal Mode On S W Reset Normal Mode On H W Reset Normal Mode On Flow Chart See Partial Area 30h ...

Page 96: ...rameter No Parameter Description This command returns the display to normal mode Normal display mode on means Partial mode off Exit from NORON by the Partial mode On command 12h Don t care Default Status Default Value Power On Sequence Normal Mode On S W Reset Normal Mode On H W Reset Normal Mode On Flow Chart See Partial Area Definition Descriptions for details of when to use this command ...

Page 97: ...o Parameter Description This command is used to recover from display inversion mode Don t care Default Status Default Value Power On Sequence Display Inversion off S W Reset Display Inversion off H W Reset Display Inversion off Flow Chart INVOFF 20h Command Parameter Display Action Mode Legend Sequential transter Display Inversion On Mode Display Inversion OFF Mode T op Left 0 0 Example Memory Dis...

Page 98: ... enter into display inversion mode To exit from Display Inversion On the Display Inversion Off command 20h should be written Don t care Default Status Default Value Power On Sequence Display Inversion off S W Reset Display Inversion off H W Reset Display Inversion off Flow Chart INVON 21h Command Parameter Display Action Mode Legend Sequential transter Display Inversion OFF Mode Display Inversion ...

Page 99: ... A maximum of 4 curves can be selected The curve is selected by setting the appropriate bit in the parameter as described in the Table GC 7 0 Parameter Curve Selected GS 1 GS 0 01h GC0 Gamma Curve 1 G2 2 Gamma Curve 1 G1 0 02h GC1 Gamma Curve 2 G1 8 Gamma Curve 2 G2 5 04h GC2 Gamma Curve 3 G2 5 Gamma Curve 3 G2 2 08h GC3 Gamma Curve 4 G1 0 Gamma Curve 4 G1 8 Note All other values are undefined Def...

Page 100: ...r into DISPLAY OFF mode In this mode the output from Frame Memory is disabled and blank page inserted This command makes no change of contents of frame memory This command does not change any other status There will be no abnormal visible effect on the display Exit from this command by Display On 29h Default Status Default Value Power On Sequence Display off S W Reset Display off H W Reset Display...

Page 101: ...ption This command is used to recover from DISPLAY OFF mode Output from the Frame Memory is enabled This command makes no change of contents of frame memory This command does not change any other status Default Status Default Value Power On Sequence Display off S W Reset Display off H W Reset Display off Flow Chart Display Off Mode DISPON Display On Mode Command Parameter Display Action Mode Legen...

Page 102: ... 0 XE 7 0 Restriction XS 15 0 always must be equal to or less than XE 15 0 When XS 15 0 or XE 15 0 is greater than maximum address like below data of out of range will be ignored 1 128X160 memory base GM 11 Parameter range 0 XS 15 0 XE 15 0 127 007Fh MV 0 Parameter range 0 XS 15 0 XE 15 0 159 009Fh MV 1 2 132X162 memory base GM 00 Parameter range 0 XS 15 0 XE 15 0 131 0083h MV 0 Parameter range 0 ...

Page 103: ...ST7735R V0 2 103 2009 08 05 Flow Chart ...

Page 104: ...0 Restriction YS 15 0 always must be equal to or less than YE 15 0 When YS 15 0 or YE 15 0 are greater than maximum row address like below data of out of range will be ignored 1 128X160 memory base GM 11 Parameter range 0 YS 15 0 YE 15 0 159 009Fh MV 0 Parameter range 0 YS 15 0 YE 15 0 127 007Fh MV 1 2 132X162 memory base GM 00 Parameter range 0 YS 15 0 YE 15 0 161 00A1h MV 0 Parameter range 0 YS ...

Page 105: ...5 Flow Chart CASET 1st parameter XS 15 0 2nd parameter XE 15 0 PASET 1st parameter YS 15 0 2nd parameter YE 15 0 RAMWR Image Data D1 7 0 D2 7 0 Dn 7 0 Any Command Command Parameter Display Action Mode Legend Sequential transter ...

Page 106: ...arameters 1 128X160 memory base GM 11 128x160x18 bit memory can be written by this command Memory range 0000h 0000h 007Fh 09Fh 2 132x162 memory base GM 00 132x162x18 bit memory can be written on this command Memory range 0000h 0000h 0083h 00A1h Default Status Default Value Power On Sequence Contents of memory is set randomly S W Reset Contents of memory is not cleared H W Reset Contents of memory ...

Page 107: ...4 B313 B312 B311 B310 Description This command is used to define the LUT for 12bits to 16bits 16 bit to 18bits color depth conversations 128 Bytes must be written to the LUT regardless of the color mode Only the values in Section 9 18 are referred In this condition 4K color 4 4 4 and 65K color 5 6 5 data input are transferred 6 R 6 G 6 B through RGB LUT table This command has no effect on other co...

Page 108: ... accordance with MADCTL setting Then D 17 0 is read back from the frame memory and the column register and the row register incremented as section 9 10 Frame Read can be cancelled by sending any other command The data color coding is fixed to 18 bit in reading function Please see section 9 8 Data color coding for color coding 18 bit cases when there is used 8 9 16 and 18 bit data lines for image d...

Page 109: ...tart Row PSL and the second the End Row PEL as illustrated in the figures below PSL and PEL refer to the Frame Memory row address counter If End Row Start Row when MADCTL ML 0 Non display area Non display area Partial display area PSL 7 0 PEL 7 0 Start row End row If End Row Start Row when MADCTL ML 1 Non display area Non display area Partial display area PSL 7 0 PEL 7 0 Start row End row If End R...

Page 110: ...ST7735R V0 2 110 2009 08 05 Flow Chart ...

Page 111: ...TEOFF 0 1 0 0 1 1 0 1 0 0 34h Parameter No Parameter Description This command is used to turn OFF Active Low the Tearing Effect output signal from the TE signal line Default Status Default Value Power On Sequence OFF S W Reset OFF H W Reset OFF Flow Chart TE Line Output ON TEOFF TE Line Output OFF Command Parameter Display Action Mode Legend Sequential transter ...

Page 112: ...ode of the Tearing Effect Output Line When TEM 0 The Tearing Effect output line consists of V Blanking information only Tvdl Tvdh Vertical time scale When TEM 1 The Tearing Effect output Line consists of both V Blanking and H Blanking information Tvdl Tvdh Vertical time scale Note During Sleep In Mode with Tearing Effect Line On Tearing Effect Output pin will be active Low Default Status Default V...

Page 113: ...IG132 Driver IC RGB 0 R G B R G B R G B SIG1 SIG2 SIG132 Driver IC RGB 1 R G B R G B SIG1 R G B R G B SIG2 R G B R G B SIG132 R G B R G B SIG1 R G B R G B SIG2 R G B R G B SIG132 LCD panel LCD panel Bit NAME DESCRIPTION MY Row Address Order MX Column Address Order MV Row Column Exchange These 3bits controls MCU to memory write read direction ML Vertical Refresh Order LCD vertical refresh direction...

Page 114: ...3rd Send last Send first Send 2nd Send 3rd Send last Top left 0 0 Top left 0 0 Default Status Default Value Power On Sequence MY 0 MX 0 MV 0 ML 0 RGB 0 MH 0 S W Reset No Change H W Reset MY 0 MX 0 MV 0 ML 0 RGB 0 MH 0 Flow Chart Command Parameter Display Action Mode Legend Sequential transter MADCTL 1st parameter B 7 0 ...

Page 115: ... HEX IDMOFF 0 1 0 0 1 1 1 0 0 0 38h Parameter No Parameter Description This command is used to recover from Idle mode on In the idle off mode 1 LCD can display 4096 65k or 262k colors 2 Normal frame frequency is applied Default Status Default Value Power On Sequence Idle Mode Off S W Reset Idle Mode Off H W Reset Idle Mode Off Flow Chart ...

Page 116: ...rame frequency is applied 3 Exit from IDMON by Idle Mode Off 38h command Color R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B4 B1 B0 Black 0xxxxx 0xxxxx 0xxxxx Blue 0xxxxx 0xxxxx 1xxxxx Red 1xxxxx 0xxxxx 0xxxxx Magenta 1xxxxx 0xxxxx 1xxxxx Green 0xxxxx 1xxxxx 0xxxxx Cyan 0xxxxx 1xxxxx 1xxxxx Yellow 1xxxxx 1xxxxx 0xxxxx White 1xxxxx 1xxxxx 1xxxxx Register Availability Status Availability Normal Mod...

Page 117: ...ST7735R V0 2 117 2009 08 05 Flow Chart Command Parameter Display Action Mode Legend Sequential transter Idle off mode IDMON Idle on mode ...

Page 118: ...l or 18 bit Pixel mode the LUT is applied to transfer data into the Frame Memory Note2 The Command 3Ah should be set at 55h when writing 16 bit pixel data into frame memory but 3Ah should be re set to 66h when reading pixel data from frame memory Please check the LUT in chapter 9 17 when using memory read function Register Availability Status Availability Normal Mode On Idle Mode Off Sleep Out Yes...

Page 119: ...parameter ID17 to ID10 LCD module s manufacturer ID NOTE See command RDDID 04h 2nd parameter Register Availability Status Availability Normal Mode On Idle Mode Off Sleep Out Yes Normal Mode On Idle Mode On Sleep Out Yes Partial Mode On Idle Mode Off Sleep Out No Partial Mode On Idle Mode On Sleep Out No Sleep In Yes Default Status Default Value Power On Sequence S W Reset H W Reset Flow Chart Comm...

Page 120: ...rameter is dummy data The 2nd parameter ID26 to ID20 LCD module driver version ID Parameter Range ID 80h to FFh ID26 to ID20 Version Changes 80h 81h 82h 83h NOTE See command RDDID 04h 3rd parameter Register Availability Status Availability Normal Mode On Idle Mode Off Sleep Out Yes Normal Mode On Idle Mode On Sleep Out Yes Partial Mode On Idle Mode Off Sleep Out No Partial Mode On Idle Mode On Sle...

Page 121: ...30 LCD module driver ID NOTE See command RDDID 04h 4th parameter Register Availability Status Availability Normal Mode On Idle Mode Off Sleep Out Yes Normal Mode On Idle Mode On Sleep Out Yes Partial Mode On Idle Mode Off Sleep Out No Partial Mode On Idle Mode On Sleep Out No Sleep In Yes Default Status Default Value Power On Sequence NV Value S W Reset NV Value H W Reset NV Value Flow Chart Comma...

Page 122: ...B2h In Idle mode 8 colors 1 1 RTNB3 RTNB2 RTNB1 RTNB0 1 1 FPB5 FPB4 FPB3 FPB2 FPB1 FPB0 FRMCTR2 10 2 2 1 1 BPB5 BPB4 BPB3 BPB2 BPB1 BPB0 RTNB set 1 line period FPB front porch BPB back porch 0 1 1 0 1 1 0 0 1 1 B3h In partial mode Full colors 1 1 RTNC3 RTNC2 RTNC1 RTNC0 1 1 FPC5 FPC4 FPC3 FPC2 FPC1 FPC0 1 1 BPC5 BPC4 BPC3 BPC2 BPC1 BPC0 1 1 RTND3 RTND2 RTND1 RTND0 1 1 FPD5 FPD4 FPD3 FPD2 FPD1 FPD0...

Page 123: ...plifier DCA adjust the booster Voltage 0 1 1 1 0 0 0 0 1 1 C3h In Idle mode 8 colors DCB9 DCB8 SAPB 2 SAPB 1 SAPB 0 APB2 APB1 APB0 PWCTR4 10 2 8 1 1 DCB7 DCB6 DCB5 DCB4 DCB3 DCB2 DCB1 DCB0 APB adjust the operational amplifier DCB adjust the booster Voltage 0 1 1 1 0 0 0 1 0 0 C4h In partial mode Full colors 1 1 DCC9 DCC8 SAPC 2 SAPC 1 SAPC 0 APC2 APC1 APC0 PWCTR5 10 2 9 1 1 DCC7 DCC6 DCC5 DCC4 DCC...

Page 124: ...XT_ R NVM control status 0 1 1 1 0 1 1 1 1 0 DEh NVM Read Command NVCTR2 10 2 15 1 1 1 0 1 0 0 1 0 1 A5 Action code 0 1 1 1 0 1 1 1 1 1 DFh NVM Write Command 1 1 NVM_ IB7 NVM _ IB6 NVM _ IB5 NVM _ IB4 NVM _ IB3 NVM _ IB2 NVM _ IB1 NVM _ IB0 1 1 NVM _ CMD7 NVM _ CMD6 NVM _ CMD5 NVM _ CMD4 NVM _ CMD3 NVM _ CMD2 NVM _ CMD1 NVM _ CMD0 NVCTR3 10 2 16 1 1 1 0 1 0 0 1 0 1 A5 Don t care Note 1 The D1h to ...

Page 125: ...3 SELV62P 2 SELV62P 1 SELV62P 0 GAMCTRP110 2 17 1 1 SELV63P 5 SELV63P 4 SELV63P 3 SELV63P 2 SELV63P 1 SELV63P 0 Gamma adjustment polarity 0 1 1 1 1 0 0 0 0 1 E1h Set 1 1 VRF0N 5 VRF0N 4 VRF0N 3 VRF0N 2 VRF0N 1 VRF0N 0 1 1 VOS0N 5 VOS0N 4 VOS0N 3 VOS0N 2 VOS0N 1 VOS0N 0 1 1 PKN0 5 PKN0 4 PKN0 3 PKN0 2 PKN0 1 PKN0 0 1 1 PKN1 5 PKN1 4 PKN1 3 PKN1 2 PKN1 1 PKN1 0 1 1 PKN2 5 PKN2 4 PKN2 3 PKN2 2 PKN2 1...

Page 126: ...ameter 1 1 RTNA3 RTNA2 RTNA1 RTNA0 2nd parameter 1 1 FPA5 FPA4 FPA3 FPA2 FPA1 FPA0 3rd parameter 1 1 BPA5 BPA4 BPA3 BPA2 BPA1 BPA0 Description Set the frame frequency of the full colors normal mode Frame rate fosc RTNA x 2 40 x LINE FPA BPA fosc 625kHz Default Status Default Value GM 1 0 00 GM 1 0 11 Power On Sequence 01h 2Ch 2Dh 01h 2Ch 2Bh S W Reset 01h 2Ch 2Dh 01h 2Ch 2Bh H W Reset 01h 2Ch 2Dh ...

Page 127: ... parameter 1 1 RTNB3 RTNB2 RTNB1 RTNB0 2nd parameter 1 1 FPB5 FPB4 FPB3 FPB2 FPB1 FPB0 3rd parameter 1 1 BPB5 BPB4 BPB3 BPB2 BPB1 BPB0 Description Set the frame frequency of the Idle mode Frame rate fosc RTNB x 2 40 x LINE FPB BPB fosc 625kHz Default Status Default Value GM 1 0 00 GM 1 0 11 Power On Sequence 01h 2Ch 2Dh 01h 2Ch 2Bh S W Reset 01h 2Ch 2Dh 01h 2Ch 2Bh H W Reset 01h 2Ch 2Dh 01h 2Ch 2B...

Page 128: ...5th parameter 1 1 FPD5 FPD4 FPD3 FPD2 FPD1 FPD0 6th parameter 1 1 BPD5 BPD4 BPD3 BPD2 BPD1 BPD0 Description Set the frame frequency of the Partial mode full colors 1st parameter to 3rd parameter are used in dot inversion mode 4th parameter to 6th parameter are used in line inversion mode Frame rate fosc RTNC x 2 40 x LINE FPC BPC fosc 625kHz Default Status Default Value GM 1 0 00 GM 1 0 11 Power O...

Page 129: ...g in full colors normal mode Normal mode on NLA Inversion setting in full Colors normal mode 0 Dot Inversion 1 Line Inversion NLB Inversion setting in Idle mode Idle mode on NLB Inversion setting in Idle mode 0 Dot Inversion 1 Line Inversion NLC Inversion setting in full colors partial mode Partial mode on Idle mode off NLC Inversion setting in full Colors partial mode 0 Dot Inversion 1 Line Inver...

Page 130: ...or testing VRHP 4 0 GVDD VRHN 4 0 GVCL 00000 4 7 00000 4 7 00001 4 65 00001 4 65 00010 4 6 00010 4 6 00011 4 55 00011 4 55 00100 4 5 00100 4 5 00101 4 45 00101 4 45 00110 4 4 00110 4 4 00111 4 35 00111 4 35 01000 4 3 01000 4 3 01001 4 25 01001 4 25 01010 4 2 01010 4 2 01011 4 15 01011 4 15 01100 4 1 01100 4 1 01101 4 05 01101 4 05 01110 4 01110 4 01111 3 95 01111 3 95 10000 3 9 10000 3 9 10001 3 8...

Page 131: ...Idle Mode Off Sleep Out Yes Normal Mode On Idle Mode On Sleep Out Yes Partial Mode On Idle Mode Off Sleep Out Yes Partial Mode On Idle Mode On Sleep Out Yes Sleep In Yes Default Status Default Value C0h Power On Sequence 82h 02h 84h S W Reset 82h 02h 84h H W Reset 82h 02h 84h Flow Chart ...

Page 132: ... VGH 00 2 AVDD VGH25 01 3 AVDD 10 3 AVDD VGH25 11 Don t use this setting reserve for testing VGLSEL 1 0 VGL 00 7 5 01 10 10 12 5 11 13 Restriction The deviation value of VGH VGL between with Measurement and Specification Max 1V VGH VGL 32V Register Availability Status Availability Normal Mode On Idle Mode Off Sleep Out Yes Normal Mode On Idle Mode On Sleep Out Yes Partial Mode On Idle Mode Off Sle...

Page 133: ...ST7735R V0 2 133 2009 08 05 Flow Chart ...

Page 134: ...ium High 101 Large 110 Reserved 111 Reserved SAP 2 0 Amount of Current in Operational Amplifier 000 Operation of the operational amplifier stops 001 Small 010 Medium Low 011 Medium 100 Medium High 101 Large 110 Reserved 111 Reserved Set the Booster circuit Step up cycle in Normal mode full colors DCA 9 8 DCA 7 6 DCA 5 4 DCA 3 2 DCA 1 0 00 BCLK 1 BCLK 1 BCLK 1 BCLK 1 BCLK 1 01 BCLK 1 5 BCLK 1 5 BCL...

Page 135: ...ST7735R V0 2 135 2009 08 05 Flow Chart ...

Page 136: ...um High 101 Large 110 Reserved 111 Reserved SAP 2 0 Amount of Current in Operational Amplifier 000 Operation of the operational amplifier stops 001 Small 010 Medium Low 011 Medium 100 Medium High 101 Large 110 Reserved 111 Reserved Set the Booster circuit Step up cycle in Idle mode 8 colors DCB 9 8 DCB 7 6 DCB 5 4 DCB 3 2 DCB 1 0 00 BCLK 1 BCLK 1 BCLK 1 BCLK 1 BCLK 1 01 BCLK 1 5 BCLK 1 5 BCLK 1 5 ...

Page 137: ...ST7735R V0 2 137 2009 08 05 Flow Chart ...

Page 138: ...edium High 101 Large 110 Reserved 111 Reserved SAP 2 0 Amount of Current in Operational Amplifier 000 Operation of the operational amplifier stops 001 Small 010 Medium Low 011 Medium 100 Medium High 101 Large 110 Reserved 111 Reserved Set the Booster circuit Step up cycle in Partial mode full colors DCC 9 8 DCC 7 6 DCC 5 4 DCC 3 2 DCC 1 0 00 BCLK 1 BCLK 1 BCLK 1 BCLK 1 BCLK 1 01 BCLK 1 5 BCLK 1 5 ...

Page 139: ...ST7735R V0 2 139 2009 08 05 Flow Chart Command Parameter Display Action Mode Legend Sequential transter PWCTR5 1st Parameter 2nd parameter ...

Page 140: ...10 0 575 22 010110 0 975 38 100110 1 375 54 110110 1 775 7 000111 0 6 23 010111 1 39 100111 1 4 55 110111 1 8 8 001000 0 625 24 011000 1 025 40 101000 1 425 56 111000 1 825 9 001001 0 65 25 011001 1 05 41 101001 1 45 57 111001 1 85 10 001010 0 675 26 011010 1 075 42 101010 1 475 58 111010 1 875 11 001011 0 7 27 011011 1 1 43 101011 1 5 59 111011 1 9 12 001100 0 725 28 011100 1 125 44 101100 1 525 ...

Page 141: ...ST7735R V0 2 141 2009 08 05 Flow Chart ...

Page 142: ...ust be enabled set to 1 VMF 4 VMF 3 0 VCOM Output Level 0 0000 VCOMS 16d 0 0001 VCOMS 15d 0 0 1110 VCOMS 2d 0 1111 VCOMS 1d 1 0000 VCOMS 1 0001 VCOMS 1d 1 0010 VCOMS 2d 1 1 1110 VCOMS 14d 1 1111 VCOMS 15d 1d 25mV 2d 50mV 3d 75mv Register Availability Status Availability Normal Mode On Idle Mode Off Sleep Out Yes Normal Mode On Idle Mode On Sleep Out Yes Partial Mode On Idle Mode Off Sleep Out Yes ...

Page 143: ...ite ID2 Value Inst Para D CX WRX RDX D17 8 D7 D6 D5 D4 D3 D2 D1 D0 HEX WRID2 0 1 1 1 0 1 0 0 0 1 D1h Parameter 1 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 Description Write 7 bit data of LCD module version to save it to NVM The parameter ID2 6 0 is LCD Module version ID Flow Chart ...

Page 144: ...e ID3 Value Inst Para D CX WRX RDX D17 8 D7 D6 D5 D4 D3 D2 D1 D0 HEX WRID3 0 1 1 1 0 1 0 0 1 0 D2h Parameter 1 1 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 Description Write 8 bit data of project code module to save it to NVM The parameter ID3 7 0 is product project ID Flow Chart ...

Page 145: ...1 1 1 0 0 1 0 0 1 D9h parameter 1 1 0 VMF_EN ID2_EN 0 0 0 0 EXT_R Description NVM control status Bit Value VMF_EN 1 Command C7h enable 0 Command C7h disable ID2_EN 1 Command D1h enable 0 Command D1h disable EXT_R Read extension command status 1 for enable 0 for disable Write Don t care Default Status Default Value D9h Power On Sequence 00h S W Reset 00h H W Reset 00h Flow Chart ...

Page 146: ...d DEH NVFCTR1 NV Memory Function Controller 2 Inst Para D CX WRX RDX D17 8 D7 D6 D5 D4 D3 D2 D1 D0 HEX NVFCTR2 0 1 1 1 0 1 1 1 1 0 DEh 1st parameter 1 1 1 1 1 1 0 1 0 1 F5 2nd parameter 1 1 1 0 1 0 0 1 0 1 A5 Description NVM Read Command NOTE Don t care Flow Chart ...

Page 147: ...0 2nd parameter 1 1 1 0 1 0 0 1 0 1 A5 Description NVM Write Command NVM_CMD 7 0 Select to Program Erase Program command 3Ah Erase command C5h NOTE Don t care Flow Chart Command Parameter Display Action Mode Legend Sequential transter Wait 20ms Modify CMD register C7h D1h D2h Enable NVM EXTC 1 CMD F1h 44h External VPP 7 5V ON NVM Program Flow Erase CMD DFh 1st Para C5h 2nd Para A5h Program CMD DFh...

Page 148: ...ELV62P 4 SELV62P 3 SELV62P 2 SELV62P 1 SELV62P 0 16th parameter 1 1 SELV63P 5 SELV63P 4 SELV63P 3 SELV63P 2 SELV63P 1 SELV63P 0 Description Register Group Positive Polarity Set up Contents High level adjustment VRF0P 5 0 Variable resistor VRHP SELV0P 5 0 The voltage of V0 grayscale is selected by the 64 to 1 selector SELV1P 5 0 The voltage of V1 grayscale is selected by the 64 to 1 selector PK0P 5...

Page 149: ...ST7735R V0 2 149 2009 08 05 Flow Chart ...

Page 150: ...ELV62N 4 SELV62N 3 SELV62N 2 SELV62N 1 SELV62N 0 16th parameter 1 1 SELV63N 5 SELV63N 4 SELV63N 3 SELV63N 2 SELV63N 1 SELV63N 0 Description Register Group Negative Polarity Set up Contents High level adjustment VRF0N 5 0 Variable resistor VRHN SELV0N 5 0 The voltage of V0 grayscale is selected by the 64 to 1 selector SELV1N 5 0 The voltage of V1 grayscale is selected by the 64 to 1 selector PK0N 5...

Page 151: ...ST7735R V0 2 151 2009 08 05 Flow Chart Command Parameter Display Action Mode Legend Sequential transter GMCTRN1 1st Parameter 2nd Parameter ...

Page 152: ...ST7735R V0 2 152 2009 08 05 11 Power Structure 11 1 Driver IC Operating Voltage Specification Fig 11 1 1 Power Booster Level ...

Page 153: ...oltage generator Charge Pump 2 Gray reference Circuit Block Gamma Source Output Circuit Block Gate Driver REGP REGP REGP REGP Vci1 AVDD AVCL AGND VDD CAVDD VDD Charge Pump 4 VDD Vci1 AVCL CVCL AVDD AGND S1 S 396 AVDD AGND GVDD VGH VGL VDDI VCOM G1 G 162 Reference Voltage generator ...

Page 154: ...2 154 2009 08 05 11 2 1 EXTERNAL COMPONENTS CONNECTION Pad Name Connection Rated Min Voltage Typical capacitance value AVDD Connect to Capacitor AVDD GND 6 3V 1 0 uF AVCL Connect to Capacitor AVCL GND 6 3V 1 0 uF ...

Page 155: ...2 V4 V4 V12 20 32 10 V4 V4 V12 24 32 V4 V4 V12 24 32 11 V4 V4 V12 28 32 V4 V4 V12 28 32 12 VINP5 VINP5 13 V12 V12 V20 4 32 V12 V12 V20 4 32 14 V12 V12 V20 8 32 V12 V12 V20 8 32 15 V12 V12 V20 12 32 V12 V12 V20 12 32 16 V12 V12 V20 16 32 V12 V12 V20 16 32 17 V12 V12 V20 20 32 V12 V12 V20 20 32 18 V12 V12 V20 24 32 V12 V12 V20 24 32 19 V12 V12 V20 28 32 V12 V12 V20 28 32 20 VINP6 VINP6 21 V20 V20 V2...

Page 156: ...4 V52 4 32 46 V44 V44 V52 8 32 V44 V44 V52 8 32 47 V44 V44 V52 12 32 V44 V44 V52 12 32 48 V44 V44 V52 16 32 V44 V44 V52 16 32 49 V44 V44 V52 20 32 V44 V44 V52 20 32 50 V44 V44 V52 24 32 V44 V44 V52 24 32 51 V44 V44 V52 28 32 V44 V44 V52 28 32 52 VINP10 VINP10 53 V52 V52 V56 1 4 V52 V52 V56 1 4 54 V52 V52 V56 2 4 V52 V52 V56 2 4 55 V52 V52 V56 3 4 V52 V52 V56 3 4 56 VINP11 VINP11 57 V56 V56 V60 1 4...

Page 157: ...ation of connection with panel direction Case 1 This is default case 1 st Pixel is at Left Top of the panel RGB filter order RGB 1st pixel IC Bump down LCD Front side CF Glass TFT Glass Case 2 1 st Pixel is at Left Top of the panel RGB filter order BGR 1st pixel IC Bump down LCD Front side CF Glass TFT Glass ...

Page 158: ...ixel is at Right Bottom of the panel RGB filter order RGB IC Bump down LCD Front side CF Glass TFT Glass 1st pixel Case 4 1 st Pixel is at Right Bottom of the panel RGB filter order BGR IC Bump down LCD Front side CF Glass TFT Glass 1st pixel ...

Page 159: ...00h 01h 02h A1h 9Fh Display direction control S W X Mirror control by MX Y Mirror control by MY XY Exchange control by MV Direction default setting H W SMX 0 SMY 0 SRGB 0 P1 P2 P3 P126 P127 P128 2 Example for SMX SMY 1 P1 P2 P3 G1 G2 G3 G4 G157 G159 G160 G158 Driver IC bump down G3 G161 G2 G160 S7 S390 00h 01h 02h 7Eh 7Fh 83h 00h 01h 02h A1h 9Fh Display direction control S W X Mirror control by MX...

Page 160: ...ST7735R V0 2 160 2009 08 05 Case2 of Resolution 132RGB x 162 GM 1 0 00 RAM size 132 x 162 x 18 bit Used Display size 132RGB x 162 1 Example for SMX SMY 0 2 Example for SMX SMY 1 ...

Page 161: ...X D CX GND VDDI P68 13 3 2 8080 Series MCU Interface for 16 bit data bus P68 0 IM2 IM1 IM0 101 80 Serial MPU 16 Bit Bus MPU ST7735R SPI4W IM2 IM1 IM0 RESX CSX D CX SCL WRX R WX D15 to D0 D17 to D16 GND RESX CSX WRX D15 to D0 RDX E RDX D CX GND VDDI P68 13 3 3 8080 Series MCU Interface for 9 bit data bus P68 0 IM2 IM1 IM0 110 80 Serial MPU 9 Bit Bus MPU ST7735R SPI4W IM2 IM1 IM0 RESX CSX D CX SCL W...

Page 162: ...800 Series MCU Interface for 8 bit data bus P68 1 IM2 IM1 IM0 100 68 Serial MPU 8 Bit Bus MPU ST7735R SPI4W IM2 IM1 IM0 RESX CSX D CX SCL WRX R WX D7 to D0 D17 to D8 GND RESX CSX R WX D7 to D0 RDX E E D CX GND VDDI P68 VDDI 13 3 6 6800 Series MCU Interface for 16 bit data bus P68 1 IM2 IM1 IM0 101 68 Serial MPU 16 Bit Bus MPU ST7735R SPI4W IM2 IM1 IM0 RESX CSX D CX SCL WRX R WX D15 to D0 D17 to D1...

Page 163: ...IM0 111 68 Serial MPU 18 Bit Bus MPU ST7735R SPI4W IM2 IM1 IM0 RESX CSX D CX SCL WRX R WX D17 to D0 VDDI GND RESX CSX R WX D17 to D0 RDX E E D CX P68 VDDI 13 3 9 3 Line serial MCU Interface IM2 IM1 IM0 000 SPI4W 0 3 Pin Serial Mode MPU ST7735R SPI4W IM2 IM1 IM0 RESX CSX RDX WRX D CX SCL SDA D0 D17 to D1 GND GND RESX CSX SCL SDA GND 13 3 10 4 Line serial MCU Interface IM2 IM1 IM0 000 SPI4W 1 4 Pin ...

Page 164: ...sion History ST7735R Specification Revision History Version Date Description V0 1 2009 07 10 First issue V0 2 2009 08 05 Modify VGH VGL PAD location P7 Add TESEL pin description P16 Modify command DFh P147 Modify AVDD range 4 5 5 1 P152 ...

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