Interrupt and trap functions
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Interrupt and trap functions
The architecture of the ST10F276 supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. These mechanisms include:
•
Normal interrupt processing
: The CPU temporarily suspends the current program
execution and branches to an interrupt service routine in order to service an interrupt
requesting device. The current program status (IP, PSW, in segmentation mode also
CSP) is saved on the internal system stack. A prioritization scheme with 16 priority
levels allows the user to specify the order in which multiple interrupt requests are to be
handled.
•
Interrupt processing via the peripheral event controller (PEC)
: A faster alternative
to normal software controlled interrupt processing is servicing an interrupt requesting
device with the ST10F276's integrated Peripheral Event Controller (PEC). Triggered by
an interrupt request, the PEC performs a single word or byte data transfer between any
two locations in segment 0 (data pages 0 through 3) through one of eight
programmable PEC Service Channels. During a PEC transfer the normal program
execution of the CPU is halted for just 1 instruction cycle. No internal program status
information needs to be saved. The same prioritization scheme is used for PEC service
as for normal interrupt processing. PEC transfers share the two highest priority levels.
•
Trap functions
: Trap functions are activated in response to special conditions that
occur during the execution of instructions. A trap can also be caused externally by the
Non-Maskable Interrupt pin NMI. Several hardware trap functions are provided for
handling erroneous conditions and exceptions that arise during the execution of an
instruction. Hardware traps always have highest priority and cause immediate system
reaction. The software trap function is invoked by the TRAP instruction, which
generates a software interrupt for a specified interrupt vector. For all types of traps the
current program status is saved on the system stack.
•
External interrupt processing
: Although the ST10F276 does not provide dedicated
interrupt pins, it allows to connect external interrupt sources and provides several
mechanisms to react on external events, including standard inputs, non-maskable
interrupts and fast external interrupts. These interrupt functions are alternate port
functions, except for the non-maskable interrupt and the reset input.
5.1
Interrupt system structure
The ST10F276 provides 56 separate interrupt nodes that may be assigned to 16 priority
levels. In order to support modular and consistent software design techniques, each source
of an interrupt or PEC request is supplied with a separate interrupt control register and
interrupt vector.
The control register contains the interrupt request flag, the interrupt enable bit, and the
interrupt priority of the associated source. Each source request is activated by one specific
event, depending on the selected operating mode of the respective device.
The only exceptions are the two serial channels of the ST10F276, where an error interrupt
request can be generated by different kinds of error. However, specific status flags which
identify the type of error are implemented in the serial channels’ control registers.