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UM0404
CAN modules
Figure 181. CPU handling of a FIFO buffer
21.9.9
Handling of interrupts
If several interrupts are pending, the CAN Interrupt Register will point to the pending
interrupt with the highest priority, disregarding their chronological order. An interrupt remains
pending until the CPU has cleared it.
The Status Interrupt has the highest priority. Among the message interrupts, the Message
Object’s interrupt priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status
Interrupt is cleared by reading the Status Register.
Read Interrupt Pointer
START
case Interrupt Pointer
0x8000h
else
0x0000h
Status Change
END
MessageNum = Interrupt Pointer
Write MessageNum to IFx Command Request
(Read Message to IFx Registers,
Reset NewDat = 0,
Reset IntPnd = 0)
Read IFx Message Control
NewDat = 1
Read Data from IFx Data A,B
EoB = 1
MessageNum = Mess 1
Yes
No
Yes
No
Message Interrupt
Interrupt Handling