The bootstrap loader
UM0404
DocID13284 Rev 2
Figure 128. UART bootstrap loader sequence
15.3.2
Entering bootstrap via UART
The ST10F276 enters BSL mode, if pin P0L.4 is sampled low at the end of a hardware
reset. In this case the built-in bootstrap loader is activated independent of the selected bus
mode. The bootstrap loader code is stored in a special Test-Flash, no part of the standard
mask ROM or Flash memory area is required for this.
After entering BSL mode and the respective initialization the ST10F276 scans the RxD0 line
to receive a zero byte, that is, one start bit, eight ‘0’ data bits and one stop bit. From the
duration of this zero byte it calculates the corresponding baudrate factor with respect to the
current CPU clock, initializes the serial interface ASC0 accordingly and switches pin TxD0
to output. Using this baudrate, an acknowledge byte is returned to the host that provides the
loaded data.
The acknowledge byte is
D5h
for the ST10F276.
15.3.3
ST10 configuration in UART BSL (RS232 or K-line)
When the ST10F276 has entered BSL mode on UART, the following configuration is
automatically set (values that deviate from the normal reset values, are
marked in bold
):
RSTIN
TxD0
Int. Boot ROM / Test-Flash BSL-routine
32 bytes
2)
3)
RxD0
CSP:IP
user software
4)
6)
P0L.4
1) BSL initialization time, > 1ms @ f
CPU
= 40 MHz.
2) Zero byte (1 start bit, eight ‘0’ data bits, 1 stop bit), sent by host.
3) Acknowledge byte, sent by ST10F276.
4) 32 bytes of code / data, sent by host.
5) Caution: TxD0 is only driven a certain time after
reception of the zero byte (1.3ms @ f
CPU
= 40 MHz).
6) Internal Boot ROM / Test-Flash.
1)
5)