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UM0404
Architectural overview
1.3.1 PLL
operation
The PLL is enabled except when P0H.[7..5] = ‘011’ or ‘001’ during reset (Direct Drive and
Prescaler modes). At Power-On, the PLL provides a stable clock signal in less than 1ms
after V
DD
has reached 5V
±
10%, even if there is no external clock signal (in this case, the
PLL will run on its basic frequency of 750 kHz to 3 MHz). Refer to datasheet for more details
about PLL characteristics.
The PLL starts synchronizing with the external clock signal as soon as it is available. Within
1ms after stable oscillations of the external clock within the specified frequency range, the
PLL will be synchronous with this clock at a frequency of F x f
XTAL
, and the PLL locks to the
external clock.
Note:
The ST10F276 is required to operate on the desired CPU clock directly after reset: make
sure that RSTIN remains active until the PLL has locked, on the contrary unlock detection
circuit immediately after reset will disconnect crystal reference clock path from the PLL
input, so the CPU clock will be provided by the PLL free running frequency.
The PLL constantly synchronizes to the external clock signal. Due to the fact that the
external frequency is 1/F’th of the PLL output frequency, the output frequency may be
slightly higher or lower than the desired frequency.
This jitter is irrelevant for longer time periods. For short periods (few CPU clock cycles), it
remains below the specified value (refer to datasheet for details).
When the PLL is detected no longer locked (no longer stable), it generates an interrupt
request (on the PLL Unlock interrupt node).
This occurs when the input clock is unstable and especially when the input clock fails
completely (for example due to a broken crystal). In this case, the synchronization
mechanism will reduce the PLL output frequency down to the PLL’s basic frequency
(750 kHz to 3 MHz). The basic frequency is still generated and allows the CPU to execute
emergency actions in case of an external clock loss.
1.3.2 Prescaler
operation
When pins P0H.[7..5] = ‘001’ during reset, the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler. Note that it is not possible to force a clock
signal through an external clock generator unless Direct Drive is selected.
The frequency of f
CPU
is half the frequency of f
XTAL
.
The PLL is still running on its basic frequency of 750 kHz to 3 MHz, and delivers the clock
signal for the Oscillator Watchdog, except if bit OWDDIS is set: in this case the PLL is
switched off.
1.3.3 Direct
drive
When pins P0H.[7..5] = ‘011’ during reset, the CPU clock is directly driven from the internal
oscillator with the input clock signal (this means f
CPU
= f
XTAL
). The maximum input clock
frequency depends on the clock signal’s duty cycle, because the minimum values for the
clock phases (TCLs) must be respected.
The PLL runs on its basic frequency of 750 kHz to 3 MHz, and delivers the clock signal for
the Oscillator Watchdog, except if bit OWDDIS is set: in this case the PLL is switched off.