DocID13284 Rev 2
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UM0404
XBUS high-speed synchronous serial interface
The Baud rate generator is clocked by f
CPU
/2. The timer is counting downwards and can be
started or stopped through the global enable bit SSCEN in register XSSCCON. Register
XSSCBR is the dual-function Baud Rate Generator/Reload register. Reading XSSCBR,
while the XSSC is enabled, returns the content of the timer. Reading XSSCBR, while the
XSSC is disabled, returns the programmed reload value. In this mode the desired reload
value can be written to XSSCBR.
Note:
Never write to XSSCBR, while the XSSC is enabled.
The formulas below calculate the resulting Baud rate for a given reload value and the
required reload value for a given Baud rate:
(XSSCBR) represents the content of the reload register, taken as unsigned 16 bit integer.
Refer to the device datasheet for a table of Baud rates, reload values and resulting bit times.
XSSCBR (E80Ah)
XBUS
Reset Value: 0000h
13.4
Error detection mechanisms
The XSSC is able to detect four different error conditions. Receive Error and Phase Error
are detected in all modes, while Transmit Error and Baud rate Error only apply to slave
mode. When an error is detected, the respective error flag is set. When the corresponding
Error Enable bit is set, also an error interrupt request will be generated. The error interrupt
handler may then check the error flags to determine the cause of the error interrupt. The
error flags are not reset automatically, but rather must be cleared by software after servicing.
This allows servicing of some error conditions via interrupt, while the others may be polled
by software.
Note:
The error interrupt handler must clear the associated (enabled) error flag(s) to prevent
repeated interrupt requests.
A
Receive Error
(Master or Slave mode) is detected, when a new data frame is completely
received, but the previous data was not read out of the receive buffer register XSSCRB.
This condition sets the error flag SSCRE and, when enabled via SSCREN, the error
interrupt request flag (see XP3INT line). The old data in the receive buffer XSSCRB will be
overwritten with the new value and is irretrievably lost.
A
Phase Error
(Master or Slave mode) is detected, when the incoming data at pin MRST1
(master mode) or MTSR1 (slave mode), sampled with the same frequency as the CPU
clock, changes between one sample before and two samples after the latching edge of the
clock signal (see “Clock Control”). This condition sets the error flag SSCPE and, when
enabled via SSCPEN, the error interrupt request flag (see XP3INT line).
A
Baud Rate Error
(Slave mode) is detected, when the incoming clock signal deviates from
the programmed Baud rate by more than 100%, it either is more than double or less than
half the expected Baud rate. This condition sets the error flag SSCBE and, when enabled
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Baud Rate
RW
Baud rate
XSSC
=
f
CPU
2 x [(XSSCBR) + 1]
XSSCBR = (
f
CPU
2 x Baud rate
XSSC
) - 1