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UM0404
Architectural overview
external RAM. Therefore it cannot store register banks and is not bit addressable. The
XRAM allows 16-bit accesses with maximum speed. A portion of the on-chip XRAM (16
Kbytes) represents the Stand-by RAM, which can be maintained biased through EA/V
STBY
pin when main supply V
DD
is turned off.
A 512 Kbyte on-chip internal Flash (IFlash)
provides for both code and constant data
storage. This memory area is connected to the CPU via a 32-bit wide bus. Thus, an entire
double-word instruction can be fetched in just one instruction cycle. Program execution from
the on-chip IFlash is the fastest of all possible alternatives.
A 320 Kbyte on-chip extended Flash
(XFlash)
is also provided for both code and constant
data storage. It is seen as an X-Peripheral and appears to the software as an external
Flash: it allows 16-bit accesses with maximum speed up to 40 MHz. A wait state should be
added when a higher CPU frequency is used.
For Special Function Registers
1024 bytes of the address space are reserved. The
standard Special Function Register area (SFR) uses 512 bytes, while the Extended Special
Function Register area (ESFR) uses the other 512 bytes. (E)SFRs are word wide registers
which are used for controlling and monitoring functions of the different on-chip units. Unused
ESFR addresses are reserved for future members of the ST10F276 family.
1.2.3 External
bus
interface
In addition to the internal memory, the application can address up to 16 Mbytes of external
memory via the external bus interface.
The integrated External Bus Controller (EBC) allows flexible access to external memory
and/or peripheral resources. For up to five address areas the bus mode (multiplexed / de-
multiplexed), the data bus width (8-bit / 16-bit) and even the length of a bus cycle (wait-
states, signal delays) can be selected independently.
This allows access to a variety of memory and peripheral components, directly and with
maximum efficiency. If the device does not run in Single Chip Mode, where no external
memory is required, the EBC can control external accesses in one of the following four
different external access modes:
•
16-/18-/20-/24-bit Addresses, and 16-bit data, de-multiplexed.
•
16-/18-/20-/24-bit Addresses, and 8-bit data, de-multiplexed.
•
16-/18-/20-/24-bit Addresses, and 16-bit data, multiplexed.
•
16-/18-/20-/24-bit Addresses, and 8-bit data, multiplexed.
The de-multiplexed bus modes use PORT1 for addresses and PORT0 for data input/output.
The multiplexed bus modes use PORT0 for both addresses and data input/output.
Important timing characteristics of the external bus interface (wait-states, ALE length and
Read/Write Delay) have been made programmable to support a wide range of different
memory peripheral types. Access to very slow memories or peripherals is supported via a
particular 'Ready' function.
To address more than 64 Kbytes of external memory, Port4 is used to generate the address
lines A16...A23. Otherwise Port4 can be used as standard I/O.
The on-chip XBUS
is an internal representation of the external bus and allows to access
integrated application-specific peripherals/modules in the same way as external
components. It provides a defined interface for these customized peripherals.