
XBUS high-speed synchronous serial interface
UM0404
DocID13284 Rev 2
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XBUS high-speed synchronous serial interface
A second High-Speed Synchronous Serial Interface (XSSC) is implemented on ST10F276.
It is mapped on XBUS interface (Address range 00’E800h-00’E8FFh) and provides flexible
high-speed serial communication between the ST10F276 and other microcontrollers,
microprocessors or external peripherals. The XSSC is enabled by setting XPEN bit 2 of
SYSCON register and bit 8 of XPERCON register.
The XSSC supports full-duplex and half-duplex synchronous communication. The serial
clock signal can be generated by the XSSC itself (master mode) or be received from an
external master (slave mode). Data width, shift direction, clock polarity and phase are
programmable. This allows communication with SPI-compatible devices. Transmission and
reception of data is double-buffered. A 16-bit Baud rate generator provides the XSSC with a
separate serial clock signal.
The high-speed synchronous serial interface can be configured in three ways, it can be
used with other synchronous serial interfaces (the ASC0/XASC in synchronous mode), or
configured like master / slave or multimaster interconnections or operate like the popular
SPI interface. It can communicate with shift registers (I/O expansion), peripherals (such as
EEPROMs) or other controllers (networking). The XSSC supports half-duplex and full-
duplex communication. Data is transmitted or received on pins MTSR1/P6.6 (Master
Transmit / Slave Receive) and MRST1/P6.7 (Master Receive / Slave Transmit). The clock
signal is output or input on pin SCLK1/P6.5. These pins are alternate functions of Port6
pins.
The main differences between SSC and XSSC are restricted to the programming model and
interrupt management, due to the constraints imposed by the XBUS with respect to the
standard ST10 peripheral bus (registers are not bit addressable, XBUS interrupt channels
sharing with other X-Peripherals). In terms of general functionality and performance, the two
modules are completely equivalent.