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UM0404
Architectural overview
1.1.2
High function 8-bit and 16-bit ALU
All standard arithmetic and logical operations are performed in a 16-bit ALU. In addition, the
condition flags for byte operations are provided from the sixth and seventh bit of the ALU
result.
Multiple precision arithmetic is provided through a 'CARRY-IN' signal to the ALU, from
previously calculated portions of the desired operation. Most of the internal execution blocks
have been optimized to perform operations on either 8-bit or 16-bit data.
Once the pipeline has been filled, one instruction is completed per instruction cycle, except
for multiply and divide. An advanced Booth algorithm has been incorporated to allow 4 bits
to be multiplied and 2 bits to be divided per instruction cycle. Thus, these operations use
two coupled 16-bit registers, MDL and MDH, and require four and nine instruction cycles,
respectively, to perform a 16-bit by 16-bit (or 32-bit by 16-bit) calculation plus one instruction
cycle to setup and adjust the operands and the result.
Even these longer multiply and divide instructions can be interrupted during their execution
to allow very fast interrupt response.
Instructions have also been provided to allow byte packing in memory while providing sign
extension of byte for word wide arithmetic operations.
The internal bus structure also allows transfers of byte or words to or from peripherals
based on the peripheral requirements.
A set of consistent flags is automatically updated in the PSW register after each arithmetic,
logical, shift, or movement operation.
These flags allow branching on specific conditions. Support for both signed and unsigned
arithmetic is provided through user-specifiable branch tests. These flags are also preserved
automatically by the CPU upon entry into an interrupt or trap routine.
All targets for branch calculations are also computed in the central ALU.
A 16-bit barrel shifter provides multiple bit shifts in a single instruction cycle. Rotate and
arithmetic shifts are also supported.
1.1.3
Extended bit processing and peripheral control
A large number of instructions are dedicated to bit processing. These instructions provide
efficient control and testing of peripherals and they enhance data manipulation. Unlike other
microcontrollers, these instructions provide direct access to two operands in the bit-
addressable space, without the need to move them into temporary flags.
The same logical instructions available for words and byte, are also supported for bit. This
allows the user to compare and modify a control bit for a peripheral, in one instruction.
Multiple bit shift instructions have been included to avoid long instruction streams of single
bit shift operations. These are also performed in a single instruction cycle. In addition, bit
field instructions have been provided to allow the modification of multiple bit from one
operand in a single instruction.
1.1.4 High
performance
branch, call and loop processing
Due to the high percentage of branching in controller applications, branch instructions have
been optimized to require one extra instruction cycle only when a branch is taken. This is
implemented by pre-calculating the target address while decoding the instruction.