ST ST10F276E, User Manual, Page: 193 / 564

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UM0404 The external bus interface
Figure 64. Memory tri-state time
8.3.4 Read / write signal delay
The ST10F276 allows the user to adjust the timing of the read and write commands to
account for timing requirements of external peripherals.
The read/write delay controls the time between the falling edge of ALE and the falling edge
of the command. Without read/write delay the falling edges of ALE and command(s) are
coincident (except for propagation delays). With the delay enabled, the command(s)
become active half a CPU clock cycle after the falling edge of ALE.
The read/write delay does not extend the memory cycle time, and does not slow down the
controller in general.
In multiplexed bus modes, however, the data drivers of an external device may conflict with
the ST10F276’s address, when the early RD signal is used. Therefore multiplexed bus
cycles should always be programmed with read/write delay.
The read/write delay is controlled via the RWDCx bit in the BUSCON registers. The
command(s) will be delayed, if bit RWDCx is ‘0’ (default after reset).
Data/instr.
Address
Address
MTTC Wait State
Bus Cycle
Segment
ALE
BUS (P0)
RD