The external bus interface
UM0404
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uses the default configuration in BUSCON0. After initializing the active registers, they are
selected and evaluated automatically by interpreting the physical address. No additional
switching or selecting is necessary during run time, except when more than the four address
windows plus the default is to be used.
Switching from de-multiplexed to multiplexed bus mode
represents a special case. The
bus cycle is started by activating ALE and driving the address to Port4 and PORT1 as usual,
if another BUSCON register selects a de-multiplexed bus. However, in the multiplexed bus
modes the address is also required on PORT0. In this special case the address on PORT0
is delayed by one CPU clock cycle, which delays the complete (multiplexed) bus cycle and
extends the corresponding ALE signal (see
).
This extra time is required to allow the previously selected device (via de-multiplexed bus) to
release the data bus, which would be available in a de-multiplexed bus cycle.
8.2.4
External data bus width
The EBC can operate on 8-bit or 16-bit wide external memory/peripherals. A 16-bit data bus
uses PORT0, while an 8-bit data bus only uses P0L, the lower byte of PORT0. This saves
on address latches, bus transceivers, bus routing and memory cost on the expense of
transfer time. The EBC can control word accesses on an 8-bit data bus as well as byte
accesses on a 16-bit data bus.
Word accesses on an 8-bit data bus
are automatically split into two subsequent byte
accesses, where the low byte is accessed first, then the high byte. The assembly of byte to
words and the disassembly of words into byte is handled by the EBC and is transparent to
the CPU and the programmer.
Byte accesses on a 16-bit data bus
require that the upper and lower half of the memory
can be accessed individually. In this case the upper byte is selected with the BHE signal,
while the lower byte is selected with the A0 signal. So the two bytes of the memory can be
enabled independent from each other, or together when accessing words.
When writing byte to an external 16-bit device, which has a single CS input, but two WR
enable inputs (for the two bytes), the EBC can directly generate these two write control
signals. This saves the external combination of the WR signal with A0 or BHE. In this case
pin WR serves as WRL (write low byte) and pin BHE serves as WRH (write high byte). Bit
WRCFG in register SYSCON selects the operating mode for pins WR and BHE. The
respective byte will be written on both data bus halves.
When reading byte from an external 16-bit device, whole words may be read and the
ST10F276 automatically selects the byte to be input and discards the other. However, care
must be taken when reading devices that change state when being read, such as FIFOs or
interrupt status registers. In this case individual byte should be selected using BHE and A0.