Debug interface
UM1585
Doc ID 023872 Rev 1
9 Debug
interface
The following debug interfaces are provided:
●
The CPU JTAG interface:
this can be used for "static" debug, meaning that it is
possible to set a breakpoint and, when the system stops, to verify the contents of the
memory and/or registers and modify them if needed.
●
The PCIe JTAG interface
: (reserved)
●
The CPU coresight interface.
(Trace 16 or 32) This can be used for "dynamic" debug.
The coresight block embedded in the SPEAr1310 chip sends all the information about
the AHB transactions during code execution to the external trace box and the external
box stores this information in a local buffer. This makes it possible to stop the CPU
activity in order to analyze the program flow. For example, if a particular data abort
occurs, you can set a breakpoint on the data abort location and then, when the
breakpoint is reached you can analyze the trace buffer. With this information, it
becomes a simple task to identify the event that produced the problem.
Table 16.
J15 JTAG connector pin-out
Pin number
Signal
1, 2
VDD3V3
4 ... 20
GND
3
nTRST
5
TDI
7
TMS
9
TCK
13
TDO
15
Powergood
11,17,19
NC
Table 17.
Debug mode selection
Switch5
Description
3
2
1
0
0
0
No debug features available
0
0
1
The ARM JTAG is connected to J15
0
1
0
ARM Trace 16bit bus available on J18 and J20
0
1
1
ARM Trace 32bit bus available on J18 and J20