SpinCore Technologies PulseBlasterESR-PRO SP18A, Owner'S Manual

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PulseBlasterESR-PRO
Data Field and OpCode
Please refer to the following table for information on the available instructions and their associated
data field argument.
OpCode
#
Inst Inst_data Function
0 CONTINUE Ignored
Program execution continues to next
instruction. See note (1) and (2) following
this table.
1 STOP Ignored
Stop execution of program. Aborts the
operation of the micro-controller with no
control of output states (all TTL values
remain from previous instruction).
Recommended that prior to the STOP
OpCode a short interval (minimum six clock
cycles) be added to set the output states as
desired.
2 LOOP
Number of desired loops. This
value must be greater than or
equal to 1.
Specify beginning of a loop. Execution
continues to next instruction. Data used to
specify number of loops
3 END_LOOP Address of beginning of loop
Specify end of a loop. Execution returns to
beginning of loop and decrements loop
counter.
4 JSR
Address of first subroutine
instruction
Program execution jumps to beginning of a
subroutine. See Note (2).
5 RTS Ignored
Program execution returns to instruction after
JSR was called. See Note (2).
6 BRANCH Address of next instruction
Program execution continues at specified
instruction
7 LONG_DELAY
Desired multiplier of the delay.
This value must be greater than
or equal to 2.
For long interval instructions. Data field
specifies a multiplier of the delay field.
Execution continues to next instruction. See
Note (2).
8 WAIT Ignored
Program execution stops and waits for
software or hardware trigger. Execution
continues to next instruction after receipt of
trigger. The latency is equal to the delay
value entered in the WAIT instruction line
plus a fixed delay of 6 clock cycles. The
WAIT OpCode may not be used by
the first instruction in memory
(1) For instructions longer than 8589 ms please use a LONG_DELAY instruction.
(2) For PulseBlasterESR-PRO-500 design 17-11, instructions with CONTINUE, JSR, RTS and
LONG_DELAY OpCodes, require a minimum instruction length of at least 6 clock-cycles (12.0 ns).
Table 7: OpCode and Data Field Description.
http://www.spincore.com 30 2019/09/26