16
M2i.30xx / M2i.30xx-exp Manual
Hardware information
Introduction
Technical Data
Analog Inputs
Trigger
Clock
BaseXIO Option
Resolution
12 bit
Input Range
software programmable
±200 mV, ±500 mV, ±1 V, ±2 V, ±5 V, ±10 V
Input Mode
fixed
bipolar, single-ended
Input Offset
software programmable
±100% of input range in steps of 1%
ADC Differential non linearity (DNL)
ADC only
±1 LSB
ADC Integral non linearity (INL)
ADC only
±1 LSB
Offset error (full speed)
after warm-up and calibration
≤
0.1% of range
Gain error (full speed)
after warm-up and calibration
≤
1% of current value
Crosstalk: 1 MHz Signal, 50
Ω
termination
all input ranges
≤
-70 dB on adjacent channels
Analog Input impedance
software programmable
50
Ω
or 1 M
Ω
|| 25 pF
Analog input coupling
fixed
DC
Over voltage protection (active card)
ranges
≤
±1 V
±5 V
Over voltage protection (active card)
ranges
>
±1 V
±50 V
Input signal with 50
Ω
termination
max 5 V rms
Channel selection
software programmable
1, 2 or 4 (maximum is model dependent)
Available trigger modes
software programmable
Channel Trigger, External, Software, Window, Pulse, Re-Arm, Or/And, Delay
Trigger level resolution
software programmable
10 bit
Trigger edge
software programmable
Rising edge, falling edge or both edges
Trigger pulse width
software programmable
0 to [64k - 1] samples in steps of 1 sample
Trigger delay
software programmable
0 to [64k - 1] samples in steps of 1 sample
Multi, Gate: re-arming time
<
4 samples (+ programmed pretrigger)
Pretrigger at Multi, ABA, Gate, FIFO
software programmable
4 up to [8176 Samples / number of active channels] in steps of 4
Posttrigger
software programmable
4 up to [8G - 4] samples in steps of 4 (defining pretrigger in standard scope mode)
Memory depth
software programmable
8 up to [installed memory / number of active channels] samples in steps of 4
Multiple Recording/ABA segment size
software programmable
8 up to [installed memory / 2 / active channels] samples in steps of 4
Trigger output delay
One positive edge after internal trigger event
Internal trigger accuracy
1 sample
External trigger accuracy
≤
100 MS/s
1 sample
External trigger accuracy
>
100 MS/s
2 samples
External trigger type (input and output)
3.3V LVTTL compatible (5V tolerant with base card hardware version > V20)
External trigger input
Low
≤
0.8 V, High
≥
2.0 V,
≥
8 ns in pulse stretch mode,
≥
2 clock periods all other modes
External trigger maximum voltage
-0.5 V up to +5.7 V (internally clamped to 5.0V, 100 mA max. clamping current)
Trigger impedance
software programmable
50 Ohm / high impedance (> 4kOhm)
External trigger output type
3.3 V LVTTL
External trigger output levels
Low
≤
0.4 V, High
≥
2.4 V, TTL compatible
External trigger output drive strength
Capable of driving 50 ohm load, maximum drive strength ±128 mA
Clock Modes
software programmable
internal PLL, internal quartz, external clock, external divided, external reference clock, sync
Internal clock range (PLL mode)
software programmable
1 kS/s to max using internal reference, 50kS/s to max using external reference clock
Internal clock accuracy
≤
20 ppm
Internal clock setup granularity
≤
1% of range (100M, 10M, 1M, 100k,...): Examples: range 1M to 10M: stepsize
≤
100k
External reference clock range
software programmable
≥
1.0 MHz and
≤
125.0 MHz
External clock impedance
software programmable
50 Ohm / high impedance (> 4kOhm)
External clock range
see „Dynamic Parameters“ table below
External clock delay to internal clock
5.4 ns
External clock type/edge
3.3V LVTTL compatible, rising edge used
External clock input
Low level
≤
0.8 V, High level
≥
2.0 V, duty cycle: 45% - 55%
External clock maximum voltage
-0.5 V up to +3.8 V (internally clamped to 3.3V, 100 mA max. clamping current)
(not 5V tolerant)
External clock output type
3.3 V LVTTL
External clock output levels
Low
≤
0.4 V, High
≥
2.4 V, TTL compatible
External clock output drive strength
Capable of driving 50 ohm load, maximum drive strength ±128 mA
Synchronization clock divider
software programmable
2 up to [8k - 2] in steps of 2
ABA mode clock divider for slow clock
software programmable
8 up to 524280 in steps of 8
BaseXIO modes
software programmable
Asynch digital I/O, 2 additional trigger, timestamp reference clock, timestamp digital inputs
BaseXIO direction
software programmable
Each 4 lines can be programmed in direction
BaseXIO input
TTL compatible: Low
≤
0.8 V, High
≥
2.0 V
BaseXIO input impedance
4.7 kOhm towards 3.3 V
BaseXIO input maximum voltage
-0.5 V up to +5.5 V
BaseXIO output type
3.3 V LVTLL
BaseXIO output levels
TTL compatible: Low
≤
0.4 V, High
≥
2.4 V
BaseXIO output drive strength
32 mA maximum current, no 50
Ω
loads
