Sorensen MML Series Operation and Programming Manual
5-52
Mnemonic Bit Value
Meaning
OC
0
1
Overcurrent
. When an overcurrent condition has
occurred on a channel, Bit 0 is set and remains set
until the overcurrent condition is removed and
LOAD:PROT:CLE is programmed.
OV
1
2
Overvoltage
. When an overvoltage condition has
occurred on a channel, Bit 1 is set and remains set
until the overvoltage condition is removed and
LOAD:PROT:CLE is programmed.
OP
2
4
Overpower.
An overpower condition has occurred
on a channel, Bit 2 is set and remains set until the
overpower condition is removed and LOAD:PROT:CLE
is programmed.
RV
3
8
Reverse voltage on input.
When a channel has a
reverse voltage applied to it, Bit 3 is set. It remains
set until the reverse voltage is removed and
LOAD:PROT:CLE is programmed.
OT
4
16
Overtemperature
. When an overtemperature condition
has occurred on a channel, Bit 4 is set and the channel
is turned off. It remains set until the channel has
cooled down well below the overtemperature trip point
and LOAD:PROT:CLE is programmed.
Table 5-5 Bit Description of Channel Status
5.11.3 Channel Status
The Channel Status register offers you one or more channel status conditions, which
indicate certain errors or faults have occurred on specific channel. Table 5-5 describes
the channel status conditions that are applied to the electronic load.
When the bits of the Channel Status Condition register are set, the corresponding
condition is true.
Program the PTR/NTR filter to select which way of a condition transition on a bit in the
Channel Status Condition register will set the corresponding bit in the
Event registers.
Reading of the Channel Status Event register resets itself to zero.
The Channel Status Enable register can be programmed to specify which channel
status event bit is logically-ORed to become the corresponding channel bit in the
Channel Summary Event register.
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