Sony SCD-XB790, Service Manual, Page: 58 / 80

58
SCD-XB790
•
MAIN BOARD IC901 CXP973064-227R (CPU)
Pin No. Pin Name I/O Description
1
MUT LOAD
O
Muting on/off control signal output to the loading motor drive “H”: muting on
2 AMUTE O
Analog muting control signal output terminal Not used
3 DOCTRL O
Digital out on/off control signal output to the digital signal processor
“L”: digital out off, “H”: digital out on
4 MUT 2D O Muting on/off control signal output to the focus/tracking coil drive “H”: muting on
5 MODE DAC I Not used
6 SP ON O Muting on/off control signal output to the spindle motor drive “H”: muting on
7 FCS JMP1 O
Focus jump 1 signal output
8 FCS JMP2 O
Focus jump 2 signal output
9 SENS CD I
Internal status (SENSE) signal input from the digital signal processor
10 — O
Not used
11 XCS IO O
Chip select signal output to the programmable logic device
12 XCS DVD O
Chip select signal output to the SACD decoder
13 VSS —
Ground terminal (digital system)
14 to 21 D0 to D7 I/O
Two-way data bus with the SACD decoder and programmable logic device
22 INT0 DVD I
Interrupt signal input from the SACD decoder
23 INT1 DVD I
Interrupt signal input from the SACD decoder
24 T SENS I
Input terminal of disc tray status detection signal from table sensor Not used
25 MIRR RF I
Mirror signal input from the digital signal processor
26 SCOR CD I
Subcode sync (S0+S1) detection signal input from the digital signal processor
27 RDY DSD I
Ready signal input from the DSD decoder “L”: ready
28 A1IN I
Input terminal of sircs remote control signal from CONTROL A1 II Not used
29 COUT CD I
Numbers of track counted signal input from the digital signal processor
30 IN SW I
Loading in switch input terminal “L”: loading in
31 OUT SW I Loading out switch input terminal “L”: loading out
32 — O Not used
33 SQSO CD I Subcode Q data input from the digital signal processor
34 DATA CD O Serial data output to the digital signal processor
35 CLOK CD O Serial data transfer clock signal output to the digital signal processor
36 XLAT CD O Serial data latch pulse signal output to the digital signal processor
37 SQCK CD O Subcode Q data reading clock signal output to the digital signal processor
38 XRST I
System reset signal input “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
39 VSS —
Ground terminal (digital system)
40 XTAL I
System clock input terminal (20 MHz)
41 EXTAL O
System clock output terminal (20 MHz)
42 VDD —
Power supply terminal (+3.3V) (digital system)
43 SPDA O
Spindle motor control signal output
44 APDO O
Output terminal for offset adjustment of APEO (
<z/.
pin of SACD decoder)
45
LOAD IN
O
Loading motor drive signal (loading in direction) output
46
LOAD OUT
O
Loading motor drive signal (loading out direction) output
47 XLAT DSD O
Serial data latch pulse signal output to the DSD decoder
48 SIN DSD I
Serial data input from the DSD decoder
49 SOUT DSD O
Serial data output to the DSD decoder and digital filter
50 SCK DSD O
Serial data transfer clock signal output to the DSD decoder and digital filter
51 MUTE DSD O
Muting on/off control signal output to the DSD decoder “H”: muting on
52 XDIS IO O Reset signal output to the programmable logic device “L”: reset
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