NWZ-A726/A726B/A728/A728B/A729
NWZ-A726/A726B/A728/A728B/A729
19
19
For Schematic Diagrams.
Note:
• All capacitors are in
μ
F unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in
Ω
and
1
/
4
W or less unless otherwise
speci
fi
ed.
•
C
: panel designation.
•
A
: B+ Line.
• Power voltage is dc 3.7 V and fed with regulated dc pow-
er supply from CN901 pin
1
and pin
2
on the MAIN
board.
• Voltages and waveform are dc with respect to ground un-
der no-signal conditions.
no mark : PLAY BACK
• Waveform is taken with a oscilloscope.
Voltages variation may be noted due to normal production
tolerances.
• Voltages are taken with a VOM (Input impedance 10
M
Ω
).
• Voltage variations may be noted due to normal production
tolerances.
• Circled number refer to waveform.
• Signal path.
F
:
AUDIO
L
:
VIDEO
• The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
form that of conventional IC.
THIS NOTE IS COMMON FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is printed in each block.)
For Printed Wiring Boards.
Note:
•
Y
: parts extracted from the conductor side.
•
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
• MAIN and SW boards are multi-layer printed board.
However, the patterns of intermediate-layers have not
been included in diagrams.
• Indication of transistor.
C
B
These are omitted.
E
Q
Caution:
Parts face side:
(SIDE A)
Pattern face side:
(SIDE B)
Parts on the parts face side seen from
the pattern face are indicated.
Parts on the pattern face side seen from
the parts face are indicated.
• Lead layouts
surface
CSP (Chip Size Package)
Lead layout of conventional IC
