NV-U74
37
• IC Pin Function Description
MAIN BOARD IC0105 GSC3ELP7975TR (GPS CONTROLLER)
Pin No.
Pin Name
I/O
Description
A1
GND_BB
-
Ground terminal
A2
GPIO1/ODO
I/O
Not used
A3
RESERVED
-
Not used
A4
GPIO0
I/O
Not used
A5
RXA
I
Serial data input from the CPU
A6
TXA
O
Serial data output to the CPU
A7
ECLK
I
External clock signal input terminal Not used
A8
SCLK
O
System clock signal output terminal Not used
A9
EA0
O
Address signal output to the
fl
ash memory
A10
VDDKPLL_O
O
Regulator output terminal for PLL
B1
RFPWRUP/GPIO8
O
Power control signal output terminal Not used
B2
XMWE
O
Write enable signal output to the
fl
ash memory
B3
VDD_FLASH
-
Power supply terminal (+2.85V)
B4
VDD_RTC
-
Power supply terminal (+1.5V)
B5
XEITO/GPIO10
I/O
External interrupt signal input/output terminal Not used
B6
EA4
O
Address signal output to the
fl
ash memory
B7
TXB
O
Serial data output terminal Not used
B8
RESERVED
-
Not used
B9
EA1
O
Address signal output to the
fl
ash memory
B10
VDDK
O
External capacitor for bypass connection terminal
C1
XCS2/GPIO14/XRTS
I/O
Chip select signal input/output terminal or request to send signal input/output terminal
Not used
C2, C3
ED1, ED10
I/O
Two-way data bus with the
fl
ash memory
C4
VDD_REG
-
Power supply terminal (+2.85V)
C5
VDD_PLL
-
Power supply terminal (+2.85V)
C6
TIMEMARK/GPIO9
O
Precise positioning service signal output to the CPU
C7
RXB
I
Serial data input terminal Not used
C8
RESERVED
-
Not used
C9
EA3
O
Address signal output to the
fl
ash memory
C10
VDDK
O
External capacitor for bypass connection terminal
D1
XMOE
O
Output enable signal output to the
fl
ash memory
D2
ED4
I/O
Two-way data bus with the
fl
ash memory
D3
XCS0
O
Chip select signal output to the
fl
ash memory
D4
VDD_BB
-
Power supply terminal (+2.85V)
D5, D6
GND_BB
-
Ground terminal
D7 to D9
EA2, EA5, EA6
O
Address signal output to the
fl
ash memory
D10
TMODE
-
Not used
E1
XCS3/GPIO15/YCLK
I/O
Chip select signal input/output terminal or Y signal input terminal Not used
E2, E3
ED9, ED8
I/O
Two-way data bus with the
fl
ash memory
E4
VDD_BB
-
Power supply terminal (+2.85V)
E5, E6
GND_BB
-
Ground terminal
E7
XWAKEUP
O
Wake-up signal output terminal Not used
E8, E9
EA7, EA8
O
Address signal output to the
fl
ash memory
E10
ROUT
O
Not used
F1
XCS1/GPIO13/XCTS
I/O
Chip select signal input/output terminal or clear to send signal input/output terminal
Not used
F2, F3
ED3, ED2
I/O
Two-way data bus with the
fl
ash memory
F4
VDD_BB
-
Power supply terminal (+2.85V)
F5, F6
GND_BB
-
Ground terminal
F7
VDD_REG
-
Power supply terminal (+2.85V)
F8, F9
EA18, EA19
O
Address signal output terminal Not used
F10
RIN
I
32.768 kHz clock signal input terminal
G1
ED0
I/O
Two-way data bus with the
fl
ash memory and RAM clear signal input from the CPU
G2 to G4
ED12, ED11, ED14
I/O
Two-way data bus with the
fl
ash memory
Summary of Contents for NV-U74
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