Sony CXD5602, User Manual

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CXD5602 User Manual
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3.21.5.3 Clock for the HPADC

CK_SCU_XOSC

CK_SCU_RC8M

CK_SCU_U32KH
One of the above three clocks is used for the sampling frequency of the HPADC.
CK_U32KH is made, in the CRG outside the SCU, by dividing CK_SCU_32K (low speed logic system clock) by
2^n (n = 0 to 15). The frequency division can be set independently from CK_SCU_U32KL of the clock for the
LPADC.
CK_SCU_XOSC is the oscillation clock of the crystal oscillator which is connected outside the LSI.
The oscillation clock of the RCOSC is input to CK_SCU_RC8M.
The API enables to select clock sources and to control selecting division ratio of CK_SCU_U32KH.
The ADCIF register actually controls to select which clock should be used for sampling frequency of the HPADC.
In addition, the frequency division of CK_SCU_XOSC and CK_SCU_RC8M can be set in the HPADC, and the
setting is controlled by the ADCIF register in the SCU as well.
The following describes the summary of input clock selection.
Table ADC-775 Input Clock Selection
Clock Source Divider Circuit Clock Port Remarks
RCRTC (RCOSC divided
by 250)
Select one number from 1, 2,
4, ...,32768 to divide
frequency
CK_SCU_32KL For LPADC
Select one number from 1, 2,
4, ...,32768 to divide
frequency
CK_SCU_32KH For HPADC
RCOSC None CK_SCU_RC8M For HPADC
XOSC None CK_SCU_XOSC For HPADC
3.21.5.4 Clock Control of the ADCIF
In the case that the HPADC in the SCU is not operated by the RCOSC while the RCOSC is ON, the power
consumption of the clock in the ADCIF can be reduced by writing “1” in RCOSC_CTRL1.
IRO_LV_SENSCLK_XEN, which is in 0x0590 region of the ADCIF.
3.21.5.5 CPU’s Clock Control to SCU
When you import the data for the ADC by using a sequencer inside the SCU, you must pay attention to the clock
supply to the SCU.