19
Pin No.
Pin Name
I/O
Pin Description
146
VSS
—
Ground
147
RESERVED
I
Fixed at L in this set.
148
VDATA3
O
Video data bus 3 output
149
VDD
—
Power supply pin (+3.3 V)
150
VDATA4
O
Video data bus 4 output
151
VSS
—
Ground
152
VDATA5
O
Video data bus 5 output
153
RESERVED
I
Fixed at L in this set.
154, 155
VDATA6, 7
O
Video data bus 6 and 7 output
156
RESERVED
I
Fixed at L in this set.
157
HSYNC
I/O
Horizontal sync input/output
158
VSYNC
I/O
Vertical sync input/output
159
NC
O
Not used. (Open)
160
VDD
—
Power supply pin (+3.3 V)
161
NC
O
Not used. (Open)
162
VSS
—
Ground
163, 164
DA-DATA1, 2
O
Serial audio samples relative to DA-BCK clock.
165
VDD2.5
—
Power supply pin (+2.5 V)
166
DA-LRCK
O
PCM left-right clock output
167
DA-BCK
O
PCM bit clock output
168
VDD2.5
—
Power supply pin (+2.5 V)
169
DA-XCK
O
Audio external frequency clock output
170
VSS
—
Ground
171
DAI-DATA
I
PCM input data, two channels.
172
DAI-LRCK
I
PCM input left-right clock
173
DAI-BCK
I
PCM input bit clock
174
RESERVED
I
Fixed at L in this set.
175
VDD
—
Power supply pin (+3.3 V)
176
A-VDD
—
Analog power supply pin (+3.3 V)
177
VCLK
I
Video clock input
178
SYSCLK
I
system clock input
179
A-VSS
—
Analog ground
180
CD-DATA
I
Serial CD data input
181
VDD
—
Power supply pin (+3.3 V)
I
Programmable polarity 16-bit word synchronization to the decoder (right channel HIGH).
—
Ground
I
CD bit clock input
I
Asserted HIGH indicated a corrupted byte.
I
Fixed at L in this set.
O
Not used. (Open)
I
Fixed at L in this set.
—
Power supply pin (+3.3 V)
O
Not used. (Open)
—
Ground
196
VSS1
—
Ground
197
VDD2.5
—
Power supply pin (+2.5 V)
198
VSS1
—
Ground
199
VSS
—
Ground
200
VSS1
—
Ground
201
HOST8SEL
I
Host select input
202 – 204
HADDR0 – 2
I
Host address bus 0 – 2 input
205
DTACKSEL
I
Data acknowledge select input
206
CS
I
Host chip select input
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