— 39 —
5-12. IC BLOCK DIAGRAMS
IC103 CXA2568M (BD BOARD)
IC301 CXD8505BQ (MAIN BOARD (2/2))
11
12
10
VC
VC
VC
VC
VC
VC
VC
VCC
VCC
RF SUMMING AMP RF_EQ_AMP
ERROR AMP
FOCUS
TRACKING
ERROR AMP
VC BUFFER
VCC
VCC
VC
VC
VC
VC
VEE
VEE
VEE
VEE
VEE
VREF
13
14
15
6
5
1
2
3
4
7
8
9
16
19
20
21
22
23
24
18
17
HOLD
LD
PD
A
B
C
D
VEE
F
E
VC
AGCVTH
AGCCONT
VCC
LC/PD
LD_ON
HOLD_SW
RF_BOT
RFTC
RF_1
RFO
RFE
FE
TE
(50%/30%
OFF)
APC PD AMP
APC LD AMP
32 31
30 29 28 27 26 25 24 23 22 21 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
34
33
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52 53 54 55 56 57 58 59 60
61 62 63 64
PLM
PLM
CLOCK
GENERATOR
TIMING
CIRCUIT
S/P
MODE
"O" DETECT
MUTE
CIRCUIT
ATT
FIR1
FIR2
FIR3
L. I. P.
(x 8)
IIR
ATT
FIR1
IIR
3RD ORDER
NOISE
SHAPER
FIR2
FIR3
L. I. P.
(x 8)
3RD ORDER
NOISE
SHAPER
AC, DC
DITHER
SYSM
ATT
SHIFT
LATCH
XINT
XDCK
XLRCK
DATA1
VSUD(D)R
DF VSS
VSUB(D)L
INAF
512FS0
256FS0
128FS0
I NV1
I NV01
I NV02
MUTE R
VSS2
R2(+)
VSS
R2(-)
VDD
VDD2
VSUB(A)R
XVSS
XVSS
X IN
X OUT
XVDD
VSUB(A)L
VDD2
VDD
L2(-)
L2(+)
VSS
VSS2
XSEL
SPLM
DFVDD1
DVDDR
VSUB(D)R
VSUB(C)R
VDD2
VDD
R1(-)
VSS
R1(+)
VSS2
201x16
MUTE L
TEST 1
TEST 2
DFVDD2
DV DDL
VSUB(D)L
VSUB(C)L
VDD2
VDD
L1(-)
L1(+)
VSS
VSS2
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