D-EJ985
10
10
SECTION 5
DIAGRAMS
5-1.
BLOCK DIAGRAM – MAIN Section (1/2) –
RF AMP,
DIGITAL SIGNAL PROCESSOR,
DIGITAL SERVO PROCESSOR,
D-RAM CONTROLLER
IC601
DIGITAL
OUT
LPF
SIGNAL
PROCESSOR
BLOCK
MEMORY
CONTROLLER,
BUS BOOST
BLOCK
SERVO
BLOCK
MDS
MDP
SENS
SCOR
SDTO
XTAI
XTAO
RFAC
XSOE
R4M
XLAT
CLOK
DOUT
XRAS
XWE
XCAS
AOUT1
AOUTL,
AOUTR
HPL,
HPR
AOUT2
LRMU
FOK
XRST
RFDC
B
A
SFDR
SRDR
FFDR
FRDR
TFDR
TRDR
D0-D3
A0-A10
WDCK
WFCK
XTAO
XTAI
E
F
89
F
92
91
A
B
88
81
RFDC
RFAC
E
LASER DIODE
OPTICAL PICK-UP BLOCK
DAX-25E
A
A
B
RF
E
F
B
RF
E
F
PD
PD
LD
LD
DETECTOR
VCC
X601
16.9344MHz
A
B
90
2, 3, 24, 25
9 – 12, 15 – 19, 21, 8
5
4
23
D-RAM
IC602
D1 – D4
A0 – A10
DOUT
XRAS
XWE
XCAS
D
E
G
H
100
99
SFDR
SRDR
96
95
FFDR
FRDR
98
97
17
18
40
41
21
22
34
32
38
36
26
24
TFDR
TRDR
M901
(SLED)
(FOCUS)
(TRACKING)
FI2
RI2
FI1
RI1
FI4
FI4
FO2
RO2
FO1
RO1
FO4
RO4
FOCUS/TRACKING COIL DRIVER
SLED MOTOR DRIVER
IC403 (1/2)
26
24
22
32
23
20
21
9
12
16
14
15
18
17
11
PREDRIVER
102
MDS
103
MDP
27
SCOR
104
2
3
24
1
18
19
20
11
13
15
21
74
72
17
C176
FOK
R4M
40
HOLD
28
CLOSE
XSOE
WDCK
SDTD
SENS
CLOK
XLA
T
XSOE
XIN
GRSCOR
FOK
MSDTO
SCOR
MSDTI
MSCK
XLA
T
+
BUFFER
IC405
SYNC
8
9
7
XRST
DATA
XLTCH
CLK
PWM
23
APWM
XBRAK
FG
+
+
U1
V1
W1
COM
U
V
W
VG
VG
SPINDLE MOTOR DRIVER
IC404
M902
(SPINDLE)
FG/FGSEL
XDRVLT
C
HOLD
OFF
VCPU B+
SL806
(OPEN)
VCPU B+
SYSTEM CONTROLLER
IC801 (1/3)
SDTO
SCK
J
L
K
SYNC
2-AXIS
DEVICE
CPU
INTERFACE
S801
HOLD
61
28
62
4, 3, 6, 5
116 – 113, 17 – 15, 13 – 11, 117
51
56
48
47
1
2
9
LRMU
XRST
HPL
HPR
F
43
44
• SIGNAL PATH
: CD PLAY (ANALOG OUT)
: CD PLAY (OPTICAL OUT)
V
U
W
6
CONTROLLER,
H BRIDGE DRIVER
2
M
CONTROL
CIRCUIT
65
13
SYSM
AMUTE
25
S804
CD LID OPEN
DETECT
VCPU B+
OPSTB
OPGSW
78
77 HG XSTB
HG GUP
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(Page 12)
(Page 12)
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(Page 11)
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