Sony BVP-550, Maintenance Manual

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6-21
IC
BVP-550
TA8129Z(TOSHIBA)
TC4S01F(TOSHIBA)CHIP PACKAGE
TC7S02FU(TOSHIBA)CHIP PACKAGE
TC7SH02FU(TOSHIBA)CHIP PACKAGE
TC4S30F(TOSHIBA)CHIP PACKAGE
TC7S86FU(TOSHIBA)CHIP PACKAGE
TC4S69F(TOSHIBA)CHIP PACKAGE
TC4SU69F(TOSHIBA)CHIP PACKAGE
TC7S04FU(TOSHIBA)CHIP PACKAGE
TC7SH04FU(TOSHIBA)CHIP PACKAGE
TC4S71F(TOSHIBA)CHIP PACKAGE
TC7S32FU(TOSHIBA)CHIP PACKAGE
TC7SH32FU(TOSHIBA)CHIP PACKAGE
TC4S11F(TOSHIBA)CHIP PACKAGE
TC7S00FU(TOSHIBA)CHIP PACKAGE
FM IF SYSTEM (DIFFERENTIAL PEAK DETECT)
— SIDE VIEW —
1
GND
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GND
V
CC
(+16 V)
BYPASS
IF
IN
BIAS
SDS
METER
SD
OUT
F
AF
OUT
MUTE
REG
DET 1 DET 2
IF
OUT
IF AMP
BYPASS
1
IF IN
2
BIAS
3
GND (IF)
4
LPF
IF OUT
16
STATION
DET
SDS
5
METER
DRIVE
MUTE
DRIVE
METER OUT
6
SD OUT
7
F
9
AF AMP
AF OUT
10
REG
V
CC
12
MUTE
11
F DET
DET 2 IN
15
REG OUT
13
DET 1 IN
14
PEAK DET
C-MOS 2-INPUT NOR GATE
(SCALE 6/1)
—TOP VIEW—
1
A
A
0
0
1
1
B
0
1
0
1
TYPE
4S01F
7S02F
7S02FU
7SH02FU
V
DD
+3 to +18V
+2 to +6V
Y
1
0
0
0
B
A
B
1
2
2
GND 3
5 V
DD
4
Y =
0 ; LOW LEVEL
1 ; HIGH LEVEL
Y = A + B = A • B
Y
4
C-MOS 2-INPUT EXCLUSIVE OR GATE
(SCALE 6/1)
—TOP VIEW—
1
2
GND 3
5 V
DD
4
A
B
2
1
4
Y
A
0
0
1
1
B
0
1
0
1
TYPE
7S86FU
7S86F
4S30F
V
DD
+2 to +6V
Y
0
1
1
0
0 ; LOW LEVEL
1 ; HIGH LEVEL
Y = A • B + A • B
+3 to +18V
C-MOS INVERTER
(SCALE 6/1)
—TOP VIEW—
1
TYPE
7S04F
7SU04F
7SU04FU
4S69F
4SU69F
7SH04FU
V
DD
+2 to +6V
2
GND 3
5 V
DD
4
A A
Y =
2 4
Y
A
0
1
Y
1
0
0 ; LOW LEVEL
1 ; HIGH LEVEL
Y = A
+3 to +18V
+2 to +5.5V
C-MOS 2-INPUT OR GATE
(SCALE 6/1)
—TOP VIEW—
1
2
GND 3
5 V
DD
4
A
B
A
B
Y =
2
1
4
Y
A
0
0
1
1
B
0
1
0
1
TYPE
7S32F
7S32FU
4S71F
7SH32FU
V
DD
+2 to +6V
Y
0
1
1
1
0 ; LOW LEVEL
1 ; HIGH LEVEL
Y = A + B = A • B
+3 to +18V
–2 to +5.5V
C-MOS 2-INPUT NAND GATE
— TOP VIEW —
TYPE
1
2
GND 3
7S00F
7S00FU
V
DD
+3 to +18 V
+2 to +6 V
A
B
Y
A
B
Y =
Y = A • B = A + B
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
0
0
1 ;
; LOW LEVEL
HIGH LEVEL
5 V
DD
4
2
1
4
4S11F
4SU11F
7SH00FU +2 to +5.5 V
(SCALE 6/1)