Sony BVP-550, Maintenance Manual

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6-17
IC
BVP-550
MN8232A(MATSUSHITA) MSM82C55A-2GS(OKI)FLAT PACKAGE
PICTURE IN PICTURE/PICTURE OUT PICTURE CONTROLLER
— TOP VIEW —
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V
DD (+5 V
)
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
DD (+5 V)
V
DD (+5 V
)
GND
GND
V
DD (+5 V)
V
DD (+5 V)
PIN
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
—
—
—
I
I
I
I
—
—
I
—
I
I
O
I
I
SIGNAL
GND
GND
VRB
TEST0
Y
RY
BY
V
DD
VRT
TEST1
V
DD
IREF
VREF
Y
COMP
VIB
PIN
No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O
O
O
—
I
I
O
I
I
I
I
O
I
—
I
—
O
SIGNAL
RY
BY
GND
RST
SCL
SDA
VPD
VCD
CKCNT
CVC
CPC
HC
GND
IREFVC
V
DD
CLAMP
PIN
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
O
I
O
I
—
—
O
O
O
O
O
O
O
O
O
O
SIGNAL
YS
HP
PPC
PVC
V
DD
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
CAS
PIN
No.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
I/O
O
O
O
O
I
I
I
—
—
I
I
I
I/O
I/O
I/O
I/O
SIGNAL
RAS
WE
DT
SC
LEV1
LEV0
DI3
V
DD
GND
DI2
DI1
DI0
DO3
DO2
DO1
DO0
9
VRT
5
Y IN
6
RY IN
7
BY IN
3
VRB
AD
CONVERTER
VERTICAL
FILTER
STORE
BUFFER
MEMORY
7
64
DO0 IN/OUT
63
DO1 IN/OUT
62
DO2 IN/OUT
61
DO3 IN/OUT
MULTIPLEXER
60
DI0 IN
59
DI1 IN
58
DI2 IN
55
DI3 IN
READ
BUFFER
MEMORY
54
LEV0 IN
53
LEV1 IN
DEMULTIPLEXER
FRAME COLOR
LEVEL
FRAME
COMPOSITE
52
SC OUT
51
DT OUT
50
WE OUT
49
RAS OUT
48
CAS OUT
47
A8 OUT
46
A7 OUT
45
A6 OUT
44
A5 OUT
43
A4 OUT
42
A3 OUT
41
A2 OUT
40
A1 OUT
39
A0 OUT
EXTERNAL MEMORY CONTROL/
ADDRESS GENERATOR
ELECTRIC
CURRENT
STORE
CONTROL
I 2 C
CONTROL
13
VREF
IN
12
IREF
IN
15
COMP
IN
+
–
16
VIB IN
14
Y OUT
DA
CONVERTER
7
6
6
17
RY
OUT
DA
CONVERTER
18
BY
OUT
DA
CONVERTER
21
SCL IN
22
SDA OUT
20
RST OUT
READ
CONTROL
SAMPLING
CLOCK
GENERATOR
28
HC IN
26
CVC IN
27
CPC OUT
32
CLAMP OUT
33
YS OUT
DISPLAY
CLOCK
GENERATOR
34
HP IN
36
PVC IN
35
CPC OUT
25
CKCNT IN
30
IREF VC IN
C-MOS PROGRAMMABLE PERIPHERAL INTERFACE
— TOP VIEW —
A0, A1
CS
D0 to 7
PA0 to 7
PB0 to 7
PC0 to 7
RD
WR ; PORT SELECT ADDRESS
; CHIP SELECT
; DATA BUS
; PORT A IN/OUT
; PORT B IN/OUT
; PORT C IN/OUT
; READ
; WRITE
A1
0
0
1
1
0
0
1
1
X
32
31
30
29
28
27
26
25
4
3
1
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
RD
WR
CS
33
RESET
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
43
42
41
40
38
37
36
35
14
15
16
18
19
20
21
23
9
10
11
13
8
7
6
5
CS
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
1
2
3
4
5
6
7
8
9
10
11
GND
0
1
X
;
;
;
LOW LEVEL
HIGH LEVEL
DON'T CARE
PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6
12 13 14 15 16 17 18 19 20 21 22
NC
V
DD
(+3 V to +6 V) NC
RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR
44 43 42 41 40 39 38 37 36 35 34
NC
33
32
31
30
29
28
27
26
25
24
23
V
DD
(+3 V to +6 V)
RESET
D0
D1
D2
D3
D4
D5
D6
D7
PB7
A0
0
1
0
1
0
1
0
1
X
CS
0
0
0
0
0
0
0
0
1
WR
1
1
1
1
0
0
0
0
X
RD
0
0
0
0
1
1
1
1
X
OPERATION
PORT A DATA BUS
PORT B DATA BUS
PORT C DATA BUS
NO OPERATION
DATA BUS PORT A
DATA BUS PORT B
DATA BUS PORT C
DATA BUS CONTROL REGISTER
HIGH IMPEDANCE
44
34
DATA
BUS
BUFFER
READ/
WRITE
CONTROL
LOGIC
D0 to D7
RD
WR
RESET
CS
A0
A1
GROUP
B
CONTROL
GROUP
A
CONTROL
GROUP
A
PORT A
PA0 to PA7
GROUP
A
PORT C
HIGHER
4-BITS
PC4 to PC7
GROUP
B
PORT C
LOWER
4-BITS
PC0 to PC3
GROUP
B
PORT B
PB0 to PB7