Sony BVP-550, Maintenance Manual

Page: 380 / 924

6-16
IC
BVP-550
MC14023BF(MOTOROLA)FLAT PACKAGE
MC74HC4053F(MOTOROLA)FLAT PACKAGE
TC74HC4053AFS(TOSHIBA)FLAT PACKAGE
MN6790S(MATSUSHITA)
C-MOS 3-INPUT NAND GATE
— TOP VIEW —
V
DD
+3 V to
+18 V
14 13 12 11 10 9 8
1 2 3 4 5 6 7
GND
A B C Y
0 1
0 1
0 1
1 1 1 0
0
1
;
;
;
LOW LEVEL
HIGH LEVEL
DON'T CARE
Y = A • B • C A + B + C =
A
B
C
Y
A
B
C
=
Y
X X
X X
X
X X
C-MOS QUAD 2-INPUT NAND GATES
—TOP VIEW—
A
B
A
B
Y = Y
14 13
V
DD
GND
12 11 10 9 8
7 6 5 4 3 2 1
A
0
0
1
1
B
0
1
0
1
TYPE
TC74AC00 TYPE
TC74VHC00
MC74HCT00N
74ACT00 TYPE
OTHER TYPES
V
DD
+2 to +5.5V
+5V
Y
1
1
1
0
0 ; LOW LEVEL
1 ; HIGH LEVEL
NOTE:
Y = A • B = A + B
+4.5 to +5.5V
+2 to +6V
C-MOS TRIPLE 2-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
— TOP VIEW —
0
0
0
0
0
0
0
0
1
CONTROL INPUTS
12
13
2
1
5
3
X0
X1
Y0
Y1
Z0
Z1
6
EN
X
Y
Z
14
15
4
0
1
X
;
;
;
LOW LEVEL
HIGH LEVEL
DON'T CARE
V
EE
*
; V
DD
– V
EE
= +3 V to +12 V
7
V
EE
C
0
0
0
0
1
1
1
1
X
B
0
0
1
1
0
0
1
1
X
Y1
IN/OUT
Y0
IN/OUT
Z1
IN/OUT
Z
IN/OUT
Z0
IN/OUT
EN
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y
IN/OUT
X
IN/OUT
X1
IN/OUT
X0
IN/OUT
A
IN
B
IN
C
IN
GND
V
DD
(+2 V to +6 V)
V
EE
*
OPEN
A
11
OPEN
B
10
OPEN
C
9
V
EE
GND
A
0
1
0
1
0
1
0
1
X
SELECT
EN
ON CHANNEL
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
X0
X1
X0
X1
OPEN
<
=
C-MOS CLOCK GENERATOR
— TOP VIEW —
4
5
14
PC1
PC2
VCO1
PC
TEST2
DIV
2
11
6
8
PC
OUT
PC1
IN
PC2
IN
DIV
OUT
MOD2
IN
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCO1
IN
TEST2
OUT
TEST1
IN
MOD1
IN
CK
OUT
D. GND
D. V
DD
(+4.5 V to +5.5 V)
A. V
DD
(+4.5 V to +5.5 V)
A. GND
PHASE
COMPARATOR
PC1 IN
4
PC2 IN
5
VCO
1
684,858,864
6
8
DIV OUT
CK OUT
1
2
11
TEST2 OUT
VCO1
IN PC
OUT
2 14
0
1
0
1
MOD1
0
0
1
1
MOD2
1/684
1/858
1/864
FREQUENCY
RATIO
OSCILLATION
STANDSTILL
VCO
CK = DIV = L
MOTE
0
1
; LOW LEVEL
; HIGH LEVEL
MC74HC00AF(MOTOROLA)FLAT PACKAGE
TC74HC00AF(TOSHIBA)FLAT PACKAGE
TC74VHC00FS(EL)(TOSHIBA)FLAT PACKAGE(SMALL)