32
AVD-S50/S50ES
Pin No.
Pin Name
I/O
Pin Description
167
XTAL
I
33.8688 MHz clock signal input terminal
168
VSS
—
Ground terminal (digital system)
169
XTL2
O
System clock output terminal (33.8688 MHz)
170
XTL1
I
System clock input terminal (33.8688 MHz)
171
VDD
—
Power supply terminal (+3.3 V) (digital system)
172 to 176
D0 to D4
I/O
Two-way data bus with the mechanism controller
Summary of Contents for AVD-S50
Page 7: ...7 AVD S50 S50ES AVD S50 AVD S50ES ...
Page 8: ...8 AVD S50 S50ES ...
Page 9: ...9 AVD S50 S50ES ...
Page 112: ...112 AVD S50 S50ES MEMO ...
Page 120: ...8 8 AVD S50 S50ES MEMO ...