SONIX SN8P26L38 User Manual Download Page 24

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SN8P26L38

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 24

Version 1.5

2.2.1 SYSTEM REGISTER

2.2.1.1SYSTEM REGISTER TABLE

PFLAG RBANK

CMP0M CMP1M

T1M

T1CL

T1CH

URTX

URRX URBRC

URTXD

URRXD

SIOM

SIOR

SIOB

P0M

PEDGE

P1W

P1M

P2M

P3M

P4M

P5M

INTRQ INTEN OSCM

WDTR

IRR

PCL

PCH

T0M

T0C

IRM

IRC

TC1M

TC1C

TC1R

STKP

P0UR

P1UR

P2UR

P3UR

P4UR

P5UR

@HL

@YZ

IRD

P1OC

STK7L STK7H STK6L STK6H STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H

2.2.1.2SYSTEM REGISTER DESCRIPTION

PFLAG = ROM page and special flag register.

R = Working register and ROM look-up data buffer.

H, L = Working, @HL and ROM addressing register.

Y, Z = Working, @YZ and ROM addressing register.

P1W = Port 1 wakeup register.

RBANK = Ram bank selection register.

CMPnM = Comparator control register.

@HL = RAM HL indirect addressing index pointer.

PEDGE = P0.0 edge direction register.

@YZ = RAM YZ indirect addressing index pointer.

PnM = Port n input/output mode register.

Pn = Port n data buffer.

P1OC = Open-drain control register.

PnUR = Port n pull-up resister control register.

INTRQ = Interrupt request register.

INTEN = Interrupt enable register.

OSCM = Oscillator mode register.

PCH, PCL = Program counter.

T0M = T0 mode register.

T0C = T0 counting register.

TC1M = TC1 mode control register.

TC1C = TC1 counter register.

TC1R = TC1 auto-reload buffer.

T1M = T1 mode register.

T1CH,L = T1 16-bit counter register.

IRM = IR output control register.

IRC = IR cycle control register.

IRR = IR auto-reload register.

IRD = IR duty control register.

WDTR = Watchdog timer clear register.

URTX = UART transmit control register.

URRX = UART receive control register.

URTXD1,2 = UART transmit data buffers.

URRXD1,2 = UART receive data buffers.

URBRC = UART baud rate control register.

SIOM = SIO mode control register.

SIOR = SIO clock rate control register.

SIOB = SIO data buffer.

STKP = Stack pointer buffer.

STK0~STK7 = Stack 0 ~ stack 7 buffer.

Summary of Contents for SN8P26L38

Page 1: ...for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX pro...

Page 2: ...R 1 0 Aug 2009 Modify comparator pin assignment description VER 1 1 Jun 2010 1 Modify UART baud rate description 2 Modify IR register name 3 Modify SYSTEM REGISTER TABLE VER 1 2 Feb 2013 Modify LQFP p...

Page 3: ...5 CHECKSUM CALCULATION 22 2 2 DATA MEMORY RAM 23 2 2 1 SYSTEM REGISTER 24 2 2 1 1 SYSTEM REGISTER TABLE 24 2 2 1 2 SYSTEM REGISTER DESCRIPTION 24 2 2 1 3 BIT DEFINITION of SYSTEM REGISTER 25 2 2 2 ACC...

Page 4: ...Diode Reset Circuit 47 3 6 4 Voltage Bias Reset Circuit 48 3 6 5 External Reset IC 49 4 SYSTEM CLOCK 50 4 1 OVERVIEW 50 4 2 CLOCK BLOCK DIAGRAM 50 4 3 FCPU INSTRUCTION CYCLE 50 4 4 OSCM REGISTER 51 4...

Page 5: ...RRUPT OPERATION CMP0 CMP1 73 6 12 SIO INTERRUPT OPERATION 74 6 13 UART INTERRUPT OPERATION 75 6 14 MULTI INTERRUPT OPERATION 76 7 I O PORT 77 7 1 OVERVIEW 77 7 2 I O PORT MODE 78 7 3 I O PULL UP REGIS...

Page 6: ...0 2 IR CONTROL REGISTER 111 10 2 1 IRM MODE REGISTER 111 10 2 2 IRC COUNTING REGISTER 111 10 2 3 IRR AUTO LOAD REGISTER 112 10 2 4 IRD IR DUTY CONTROL REGISTER 113 10 2 5 IR OUTPUT OPERATION SEQUENCE...

Page 7: ...KIT 128 15 2 ICE AND EV KIT APPLICATION NOTIC 129 16 OTP PROGRAMMING PIN 130 16 1 THE PIN ASSIGNMENT OF EASY WRITER TRANSITION BOARD SOCKET 130 16 2 PROGRAMMING PIN MAPPING 131 17 MARKING DEFINITION...

Page 8: ...rupt input P0 0 P0 1 One channel UART interface External Interrupt trigger edge P0 0 controlled by PEDGE register Four system clocks External high clock RC type up to 8 MHz 3 Level LVD External high c...

Page 9: ...OL EXTERNAL HIGH OSC ACC INTERNAL LOW RC TIMING GENERATOR RAM SYSTEM REGISTERS LVD Low Voltage Detector WATCHDOG TIMER TIMER COUNTER P0 P3 P1 PWM 1 BUZZER 1 ALU PC FLAGS IR OTP ROM PWM1 BZ1 P2 INTERNA...

Page 10: ...32 P4 4 P2 0 18 31 P4 3 P2 1 19 30 P4 2 P2 2 CM0N 20 29 P4 1 P2 3 CM0P 21 28 P4 0 P2 4 CM0O 22 27 VDD P2 5 CM1N 23 26 VSS P2 6 CM1P 24 25 P2 7 CM1O SN8P26L38F LQFP 48 pins P0 4 XOUT P0 3 XIN P0 2 RST...

Page 11: ...I O P2 2 Bi direction pin Schmitt trigger structure as input mode Built in pull up resisters CM0N The negative input pin of comparator P2 3 CM0P I O P2 3 Bi direction pin Schmitt trigger structure as...

Page 12: ...rection pin Schmitt trigger structure as input mode Built in pull up resisters IROUT IR signal output pin P5 7 5 I O P5 7 5 Bi direction pin Schmitt trigger structure as input mode Built in pull up re...

Page 13: ...parator Negative Input Comparator Positive Pin Pull Up Resistor Output Latch Pin PnUR PnM Input Bus Output Bus CMnEN Comparator Positive Input CMnREF Comparator Output Pin Pull Up Resistor Output Latc...

Page 14: ...vector User interrupt vector 0009H General purpose area User program 000FH 0010H 0011H 1FFCH End of user program 1FFDH Reserved 1FFEH 1FFFH The ROM includes Reset vector Interrupt vector General purp...

Page 15: ...ernal reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset status from NT0 N...

Page 16: ...ing example shows the way to define the interrupt vector in the program memory Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is a unique buffer and only one level...

Page 17: ...am User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from buffers RETI End of interrup...

Page 18: ...t lookup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z overflow FFH 00 Y Y 1 NOP MOVC To lookup data...

Page 19: ...ord 16 bits data DW 5105H DW 2012H The other example of look up table is to add Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register by B0ADD ADD in...

Page 20: ...ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value and not change Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary B0ADD PCL A PCL PCL ACC PCH...

Page 21: ...egin from next RAM boundary 0x0100 Example JMP_A operation Before compiling program ROM address B0MOV A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X00FD JMP A0POINT...

Page 22: ...end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end of code AAA INC...

Page 23: ...tly Under one bank condition and need to access the other bank RAM setup the RBANK register is necessary Sonix provides Bank 0 type instructions e g b0mov b0add b0bts1 b0bset to control Bank 0 RAM in...

Page 24: ...er HL RAM HL indirect addressing index pointer PEDGE P0 0 edge direction register YZ RAM YZ indirect addressing index pointer PnM Port n input output mode register Pn Port n data buffer P1OC Open drai...

Page 25: ...7M P56M P55M P54M P53M P52M P51M P50M R W P5M I O direction 0C8H SIOIRQ TC1IRQ T1IRQ T0IRQ RXIRQ TXIRQ P01IRQ P00IRQ R W INTRQ 0C9H SIOIEN TC1IEN T1IEN T0IEN RXIEN TXIEN P01IEN P00IEN R W INTEN 0CAH C...

Page 26: ...10 S2PC9 S2PC8 R W STK2H 0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R W STK1L 0FDH 1 1 1 S1PC12 S1PC11 S1PC10 S1PC9 S1PC8 R W STK1H 0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 R W S...

Page 27: ...by B0MOV instruction during the instant addressing mode Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Write ACC data f...

Page 28: ...by external Reset Pin Bit 5 LVD30 LVD 2 8V operating flag and only support LVD code option is LVD_H 0 Inactive VDD 2 8V 1 Active VDD 2 8V Bit 4 LVD24 LVD 2 4V operating flag and only support LVD code...

Page 29: ...Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are nine instru...

Page 30: ...C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results underflow of 0...

Page 31: ...hree instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automatically If PCL...

Page 32: ...it 0 L LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 Read Write R W R W R W R W R W R W R W R W After reset X X X X X X X X Example If want to read a data from RAM address 20H of bank_0 it can use i...

Page 33: ...er reset 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 Read Write R W R W R W R W R W R W R W R W After reset Example Uses Y Z register as the...

Page 34: ...te data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6 Bit 5 Bit 4 Bit...

Page 35: ...gister 2 3 2 DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC Example Move 0x12 RAM location data into ACC B0MOV A 12H To get a content of RAM l...

Page 36: ...are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program counter PC data...

Page 37: ...ine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...

Page 38: ...0 STK2H STK2L 4 0 1 1 STK3H STK3L 5 0 1 0 STK4H STK4L 6 0 0 1 STK5H STK5L 7 0 0 0 STK6H STK6L 8 1 1 1 STK7H STK7L 8 1 1 0 Stack Over error There are Stack Restore operations correspond to each push o...

Page 39: ...stal resonator e g 4M for external high clock oscillator Watch_Dog Always_On Watchdog timer is always on enable even in power down and green mode Enable Enable watchdog timer Watchdog timer stops in p...

Page 40: ...ption 0 0 Watchdog reset Watchdog timer overflow 0 1 Reserved 1 0 Power on reset and LVD reset Power voltage is lower than LVD detecting level 1 1 External reset External reset pin detect low level st...

Page 41: ...er by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is reset After wa...

Page 42: ...elow area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some conditions DC application Th...

Page 43: ...ltage and System Reset The LVD low voltage detector is built in Sonix 8 bit MCU to be brown out reset protection When the VDD drops and is below LVD detect voltage the LVD would be triggered and the s...

Page 44: ...able Available 2 4V Flag Available 2 4V Reset Available 2 8V Flag Available LVD_L If VDD 1 8V system will be reset Disable LVD24 and LVD28 bit of PFLAG register LVD_M If VDD 1 8V system will be reset...

Page 45: ...g until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and the system return to normal mode after reset sequence This method also can improve brown out reset co...

Page 46: ...ystem keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is su...

Page 47: ...Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrical Over str...

Page 48: ...value to conform the application In the circuit diagram condition the MCU s reset pin level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and the voltage low...

Page 49: ...VCC GND RST Reset IC VDD VSS RST Bypass Capacitor 0 1uF The external reset circuit also use external reset IC to enhance MCU reset performance This is a high cost and good effect solution By different...

Page 50: ...CLOCK BLOCK DIAGRAM Fhosc Fcpu Fhosc 1 Fhosc 8 Flosc Fcpu Flosc 4 CPUM 1 0 XIN XOUT STPHX HOSC Fcpu Code Option Fosc Fosc CLKMD Fcpu HOSC High_Clk code option Fhosc External high speed clock Internal...

Page 51: ...CLK IHRC_8M STPHX 1 disables internal high speed RC type oscillator High_CLK IHRC_RTC STPHX 1 disables internal high speed RC type oscillator and external 32768Hz crystal High_CLK RC 4M 8M 32K STPHX 1...

Page 52: ...XIN XOUT pins are general purpose I O pins IHRC_RTC High clock is internal 8MHz oscillator RC type XIN XOUT pins are connected with external 32768Hz crystal ceramic oscillator for RTC clock source Th...

Page 53: ...x 4MHz 32K option is for low speed ex 32768Hz MCU VCC GND C 20pF XIN XOUT VDD VSS C 20pF CRYSTAL Note Connect the Crystal Ceramic and C as near as possible to the XIN XOUT VSS pins of micro controller...

Page 54: ...rnal clock signal input to be system clock is by RC option of High_Clk code option The external clock signal is input from XIN pin XOUT pin is general purpose I O pin MCU VCC GND VSS VDD XIN XOUT Exte...

Page 55: ...watchdog disable If system is in 455K mode and watchdog disable only 455K oscillator actives and system is under low power consumption Example Stop internal low speed oscillator by power down mode B0...

Page 56: ...E NORMAL SLOW GREEN POWER DOWN SLEEP REMARK EHOSC Running By STPHX By STPHX Stop IHRC Running By STPHX By STPHX Stop ILRC Running Running Running Stop EHOSC with RTC Running By STPHX Running Stop IHRC...

Page 57: ...d and full functions are controllable The system rate is low speed Flosc 4 The internal low speed RC type oscillator actives and the high speed oscillator is controlled by STPHX 1 In slow mode to stop...

Page 58: ...nsets to normal mode after wake up If inserting green mode from slow mode the system insets to slow mode after wake up The green mode wake up source are P0 P1 level change trigger and unique time over...

Page 59: ...set T0 clock Fcpu 64 MOV A 74H B0MOV T0C A To set T0C initial value 74H To set T0 interval 10 ms B0BCLR FT0IEN To disable T0 interrupt service B0BCLR FT0IRQ To clear T0 interrupt request B0BSET FT0ENB...

Page 60: ...IME When the system is in power down mode sleep mode the high clock oscillator stops When waked up from power down mode MCU waits for 2048 external high speed oscillator clocks as the wakeup time to s...

Page 61: ...stem up to normal mode The Port 0 and Port 1 have wakeup function Port 0 wakeup function always enables but the Port 1 is controlled by the P1W register 0C0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...

Page 62: ...ping other interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept the next interrupts request Most of the interrupt request signals are stored in INTRQ regi...

Page 63: ...External P0 1 interrupt INT1 control bit 0 Disable INT1 interrupt function 1 Enable INT1 interrupt function Bit 2 TXIEN UART transmit interrupt control bit 0 Disable UART transmit interrupt function 1...

Page 64: ...NT0 interrupt request Bit 1 P01IRQ External P0 1 interrupt INT1 request flag 0 None INT1 interrupt request 1 INT1 interrupt request Bit 2 TXIRQ UART transmit interrupt request flag 0 None UART transmi...

Page 65: ...pt requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 level 0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE STKPB2 STKPB1 STKPB0 Read Wri...

Page 66: ...s save and load ACC PFLAG data into buffers and avoid main routine error after interrupt service routine finishing Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is...

Page 67: ...and the trigger edge direction matches interrupt edge configuration the trigger edge will be latched and the system executes interrupt service routine fist after wake up 0BFH Bit 7 Bit 6 Bit 5 Bit 4 B...

Page 68: ...the P01IRQ is set to be 1 Users need to be cautious with the operation under multi interrupt situation Note The interrupt trigger direction of P0 1 is falling edge Example INT1 interrupt request setup...

Page 69: ...0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 74H Set T0C initial value 74H B0MOV T0C A Set T0 interval 10 ms B0BSET FT0IEN...

Page 70: ...6us delay time 2 In RTC mode don t reset T0C in interrupt service routine Example T0 interrupt service routine with RTC function ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save...

Page 71: ...upt request setup B0BCLR FT1IEN Disable T1 interrupt service B0BCLR FT1ENB Disable T1 timer MOV A 20H B0MOV T1M A Set T1 clock Fcpu 64 and falling edge trigger CLR T1C B0BSET FT1IEN Enable T1 interrup...

Page 72: ...le TC1 interrupt request setup B0BCLR FTC1IEN Disable TC1 interrupt service B0BCLR FTC1ENB Disable TC1 timer MOV A 20H B0MOV TC1M A Set TC1 clock Fcpu 64 MOV A 74H Set TC1C initial value 74H B0MOV TC1...

Page 73: ...CM0IEN Comparator 0 interrupt function control bit 0 Disable 1 Enable Bit 5 CM0IRQ Comparator 0 interrupt request bit 0 Non comparator interrupt request 1 Announce comparator interrupt request 09DH Bi...

Page 74: ...nterrupt vector even when the SIOIEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation Example SIO interrupt request setup B0BSET FSIOIEN Enable SIO interrupt...

Page 75: ...to be cautious with the operation under multi interrupt situation Example UART receive and transmit interrupt request setup B0BSET FRXIEN Enable UART receive interrupt service B0BCLR FRXIRQ Clear UAR...

Page 76: ...conditions two things need to be taking care of One is to set the priority for these interrupt requests Two is using IEN and IRQ flags to decide which interrupt to be executed Users have to check inte...

Page 77: ...ion Reset VPP HV OTP Programming P0 3 I O XIN AC High_CLK code option IHRC_RTC RC 32K 4M 8M P0 4 I O XOUT AC High_CLK code option IHRC_RTC 32K 4M 8M P2 2 I O CM0N AC CM0EN 1 P2 3 I O CM0P AC CM0EN 1 C...

Page 78: ...it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3M P33M P32M P31M P30M Read Write R W R W R W R W After reset 0 0 0 0 0C4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4M P47M P46M P45M P44M P43M...

Page 79: ...P22R P21R P20R Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 0E3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3UR P33R P32R P31R P30R Read Write W W W W After reset 0 0 0 0 0E4H Bit 7 Bi...

Page 80: ...it 0 P1OC P52OC P51OC P50OC P33OC P32OC P11OC P10OC Read Write W W W W W W W After reset 0 0 0 0 0 0 0 Bit 0 P10OC P1 0 open drain control bit 0 Disable open drain mode 1 Enable open drain mode Bit 1...

Page 81: ...r high B0BSET P10M Enable P1 0 output mode MOV A 01H Enable P1 0 open drain function B0MOV P1OC A Note P1OC is write only register Setting P10OC must be used MOV instructions Example Disable P1 0 to o...

Page 82: ...0 P3 P33 P32 P31 P30 Read Write R W R W R W R W After reset 0 0 0 0 0D4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4 P47 P46 P45 P44 P43 P42 P41 P40 Read Write R W R W R W R W R W R W R W R W...

Page 83: ...unction Watchdog timer actives in normal mode and slow mode In power down mode and green mode the watchdog timer stops Always_On Enable watchdog timer function The watchdog timer actives and not stop...

Page 84: ...routine That can improve main routine fail Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An operatio...

Page 85: ...ncy RTC timer Generates interrupts at real time intervals based on the selected clock source RTC function is only available in High_Clk code option IHRC_RTC Green mode wakeup function T0 can be green...

Page 86: ...ad Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 0 T0TB RTC clock source control bit 0 Disable RTC T0 clock source from Fcpu 1 Enable RTC Bit 6 4 T0RATE 2 0 T0 internal clock select bits 000 fcp...

Page 87: ...initial value 256 T0 interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H The basic timer table interval time of T0 T0RATE T0CLOCK High speed mode Fcpu 4MHz 4 Low speed m...

Page 88: ...s disabled B0BCLR FT0IRQ T0 interrupt request flag is cleared Set T0 timer rate MOV A 0xxx0000b The T0 rate control bits exist in bit4 bit6 of T0M The value is from x000xxxxb x111xxxxb B0MOV T0M A T0...

Page 89: ...le up counting timer Generates interrupts at specific time intervals based on the selected clock frequency Fcpu T1 Rate Fcpu 2 Fcpu 256 T1ENB CPUM0 1 T1C 16 Bit Binary Up Counting Counter T1 Time Out...

Page 90: ...l value 65536 T1 interrupt interval time input clock Example To set 10ms interval time for T1 interrupt High clock is external 4MHz Fcpu Fosc 4 Select T1RATE 010 Fcpu 64 T1C initial value 65536 T1 int...

Page 91: ...V A T1CH Read T1CH first and T1C low byte data exported to T1CL B0MOV A T1CL Read T1CL data from buffer Note Read T1CH first when reading T1C 16 bit buffer Example Writing and setting T1C 16 bit buffe...

Page 92: ...mer B0BCLR FT1IEN T1 interrupt function is disabled B0BCLR FT1IRQ T1 interrupt request flag is cleared Set T1 timer rate MOV A 0xxx0000b The T1 rate control bits exist in bit4 bit6 of T1M The value is...

Page 93: ...t interrupt service TC1 overflow time is 0xFF to 0X00 normally Under PWM mode TC1 overflow is decided by PWM cycle controlled by ALOAD1 and TC1OUT bits The main purposes of the TC1 timer is as followi...

Page 94: ...ol bit Only valid when PWM1OUT 0 0 Disable P5 3 is I O function 1 Enable P5 3 is output TC1OUT signal Bit 2 ALOAD1 Auto reload control bit Only valid when PWM1OUT 0 0 Disable TC1 auto reload function...

Page 95: ...256 count 1 0 1 64 0x00 0x3F xx000000b xx111111b Overflow per 64 count 1 1 0 32 0x00 0x1F xxx00000b xxx11111b Overflow per 32 count 1 1 1 16 0x00 0x0F xxxx0000b xxxx1111b Overflow per 16 count 1 256 0...

Page 96: ...Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of TC1R initial value is as following TC1R initial value N TC1 interrupt interval time input clock N is TC1 overflow boundary numbe...

Page 97: ...as following 1 2 3 4 1 2 3 4 TC1 Overflow Clock TC1OUT Buzzer Output Clock Example Setup TC1OUT output from TC1 to TC1OUT P5 3 The external high speed clock is 4MHz Fcpu Fosc 4 1MIPS The TC1OUT frequ...

Page 98: ...SET FTC1CKS Select TC1 external clock source Set TC1 timer auto load mode B0BCLR FALOAD1 Enable TC1 auto reload function or B0BSET FALOAD1 Disable TC1 auto reload function Set TC1 interrupt interval t...

Page 99: ...en the counter reaches zero the PWM output is forced high The low to high ratio duty of the PWM1 output is TC1R 256 64 32 16 ALOAD1 TC1OUT PWM duty range TC1C valid value TC1R valid bits value MAX PWM...

Page 100: ...M DUTY In PWM mode the frequency of TC1IRQ is depended on PWM duty range From following diagram the TC1IRQ frequency is related with PWM duty TC1C Value PWM1 Output Duty Range 0 255 PWM1 Output Duty R...

Page 101: ...MOV TC1M A Set the TC1 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 B0MOV TC1C A B0MOV TC1R A B0BCLR FTC1OUT Set duty range as 0 256 255 256 B0BCLR FALOAD1 B0BSET FPWM1OUT Enable PWM1 output to...

Page 102: ...l output logic Low If TC1C is changed in certain period the PWM duty will change immediately If TC1R is fixed all the time the PWM waveform is also the same TC1C overflow and TC1IRQ set TC1C TC1R 0xFF...

Page 103: ...outputs correct duty In period 4 the new TC1R value is smaller than the old TC1R value If setting new TC1R is before PWM output low system is getting TC1C TC1R result and making PWM output low In the...

Page 104: ...9V CM1OEN CM1EN CM1EN CM1REF CM1N CM1O CM1P Comparator 0 Comparator 1 Comparator Reference Voltage CM0OUT Flag CM1IRQ CM1IEN Comparator 1 Interrupt CM1OUT Flag Comparator 0 Pin assignment CM0P Compara...

Page 105: ...omparator Internal Logic CMnN CMnO GPIO CMnP GPIO Comparator Comparator Internal Logic Internal Reference Voltage CMnEN 1 CMnOEN 1 CMnREF 0 CMnEN 1 CMnOEN 1 CMnREF 1 CMnEN 1 CMnOEN 0 CMnREF 0 CMnEN 1...

Page 106: ...arator interrupt request and it is cleared by program 0 No comparator interrupt request 1 Comparator interrupt request occurs when CM0P voltage or comparator 0 reference voltage is larger than CM0N vo...

Page 107: ...m 0 No comparator interrupt request 1 Comparator interrupt request occurs when CM1P voltage or comparator 1 reference voltage is larger than CM1N voltage Bit 4 CM1OEN Comparator 1 output pin control b...

Page 108: ...y 2 0V Example Use 2 ch comparators to detect battery status The battery voltage less than 2 2V is low battery status The battery voltage less than 2 0V is no battery status This case is polling CMnOU...

Page 109: ...O LTD Page 109 Version 1 5 JMP LowBat Is low battery status go to low battery routine JMP NoBat Is no battery status go to no battery routine Low battery process LowBat JMP Main Return to main loop No...

Page 110: ...r clock source is only from Fhosc system high clock source eg IHRC_8M 4MHz or 455KHz crystal If Fhosc is 4MHz the IR counter clock rate is 4MHz IR timer only generate IR output and no interrupt functi...

Page 111: ...arry signal output control bit 0 Disable IROUT pin is output low status 1 Enable IROUT pin outputs IR carry signal Note IR carry output condition is IREN 1 and CREN 1 If CREN 1 and IREN 0 the IROUT pi...

Page 112: ...tored in 1 st buffer Until IR overflow occurs the new value moves to real IRR buffer 0CDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRR IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 Read Write W W W W...

Page 113: ...RD2 IRD1 IRD0 Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of IRD initial value is as following IRD initial value IRR 256 IRR 1 IR duty Example Set IRD for 38KHz IR and duty is...

Page 114: ...TPUT OPERATION SEQUENCE Set IRC and IRR for IR cycle MOV A IRCYCVAL IRC IRR value for IR cycle MOV IRC A MOV IRR A Set IRD for IR duty MOV A IRDUTYVAL IRD value for IR duty MOV IRD A Enable IR output...

Page 115: ...n such as transmit receive clock rate data transfer direction SIO clock idle status and clock control phase and starting this circuit This SIO circuit will transmit or receive 8 bit data automatically...

Page 116: ...3 bit2 bit1 bit0 SCK idle status Low The transfer first bit MSB SCK data transfer edge Falling edge 0 1 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCK idle status High The transfer first bit MSB SCK da...

Page 117: ...SENB select CPOL and CPHA bits These bits control SIO pins mode 11 3 SIOM MODE REGISTER SIOM initial value 0000 0000 0B4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIOM SENB START SRATE1 SRATE0...

Page 118: ...in structure controlled by P1OC register 11 4 SIOB DATA BUFFER SIOB initial value 0000 0000 0B6H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIOB SIOB7 SIOB6 SIOB5 SIOB4 SIOB3 SIOB2 SIOB1 SIOB0 Re...

Page 119: ...IOR is designed for the SIO counter to reload the counted value when end of counting It is like a post scaler of SIO clock source and let SIO has more flexible to setting SCK range Users can set the S...

Page 120: ...n parity bit End of Transfer interrupt 12 2 UART OPERATION The UART RX and TX pins are shared with GPIO When UART enables RXDEN 1 TXDEN 1 the UART shared pins transfers to UART purpose and disable GPI...

Page 121: ...starting The start bit is a simple format which is high to low edge change and the duration is one bit period The start bit is easily recognized by the receiver 8 bit Data The data format is 8 bit len...

Page 122: ...it0 Start bit7 Stop Gap Idle Status Idle Status The First Data Byte Low Byte The Second Data Byte High Byte 2 Byte Transfer Format without Parity Bit The UART supports interrupt function RXIEN TXIEN a...

Page 123: ...control bit 0 UART RX parity bit format is even parity 1 UART RX parity bit format is odd parity Bit 2 URXPC UART RX parity bit checking status bit 0 UART RX parity bit checking is error 1 UART RX pa...

Page 124: ...PCS 2 0 000b 001b UART Baud Rate Fhosc 2 PreScaler Divider 1 16 Pre scaler UPCS 2 0 010b 111b UART Baud Rate Fhosc 2 PreScaler Divider 16 Baud Rate Fhosc 16MHz Fhosc 8MHz Fhosc 4MHz UPCS 2 0 UDIV 4 0...

Page 125: ...R W R W R W R W After Reset 0 0 0 0 0 0 0 0 Bit 7 0 URTXD2 UART transmitted data buffer byte 2 URRXD1 initial value 0000 0000 0A9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URRXD1 URXD17 URXD16...

Page 126: ...M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 N R RRC M A RRC M 1 O RRCM M M RRC M 1 N C RLC M A RLC M 1 E RLCM M M RLC M...

Page 127: ...port input leakage current Ilekg Pull up resistor disable Vin Vdd 2 uA I O output source current IoH Vop Vdd 0 5V 8 10 mA sink current IoL Vop Vss 0 5V 8 12 INTn trigger pulse width Tint0 INT0 interru...

Page 128: ...interface GPIO interface and EV chip module EV chip module Emulate comparator function The schematic of SN8P26L38 EV kit is as following CON1 JP10 ICE interface connected to SN8ICE2K JP1 EV Kit power...

Page 129: ...are shared with P2 GPIO pins In ICE environment the comparator pins isn t connected with GPIO pin The Comparator emulation is from the SN8P26L34 EV chip of SN8P26L38 EV kit For comparator emulation i...

Page 130: ...3 46 DIP46 D0 8 7 D1 DIP4 4 45 DIP45 D2 10 9 D3 DIP5 5 44 DIP44 D4 12 11 D5 DIP6 6 43 DIP43 D6 14 13 D7 DIP7 7 42 DIP42 VPP 16 15 VDD DIP8 8 41 DIP41 RST 18 17 HLS DIP9 9 40 DIP40 ALSB PDB 20 19 DIP10...

Page 131: ...SN8P26L38F EZ Writer Connector OTP IC JP3 Pin Assignment Number Name Number Pin Number Pin Number Pin Number Pin 1 VDD 27 48 VDD 21 42 VDD 2 GND 1 26 VSS 20 43 VSS 3 CLK 40 P5 0 34 P5 0 4 CE 5 PGM 10...

Page 132: ...bit MCU for order or obtain information This definition is only for Blank OTP MCU 17 2 MARKING INDETIFICATION SYSTEM Title SONiX 8 bit MCU Production ROM Type P OTP A MASK Material B PB Free Package...

Page 133: ...e SN8P26L38FB OTP 26L38 LQFP 0 70 PB Free Package SN8P26L38PG OTP 26L38 PDIP 0 70 Green Package SN8P26L38FG OTP 26L38 LQFP 0 70 Green Package S8P26L38W OTP 26L38 Wafer 0 70 SN8P26L38H OTP 26L38 Dice 0...

Page 134: ...DIP 48 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 220 5 588 A1 0 015 0 381 A2 0 150 0 155 0 160 3 810 3 937 4 064 D 2 400 2 450 2 550 60 960 62 230 64 770 E 0 600 15 240 E1 0 540 0 545 0 550 13 7...

Page 135: ...MBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 063 1 6 A1 0 002 0 006 0 05 0 15 A2 0 053 0 057 1 35 1 45 c1 0 004 0 006 0 09 0 16 D 0 354 BSC 9 00 BSC D1 0 276 BSC 7 00 BSC E 0 354 BSC 9 00 BSC E1 0 276 BS...

Page 136: ...butors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or...

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SONIX SN8P26L38, User Manual

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