SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 71
Version 2.0
4.7 PMU REGISTERS
Base Address: 0x4003 2000
4.7.1
Backup registers 0~15 (PMU_BKP0~15)
Address Offset: 0x0, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0x24, 0x28, 0x2C, 0x30, 0x34, 0x38, 0x3C
The backup registers retain data through the Deep power-down mode when power is still applied to the VDD pin but
the chip has entered Deep power-down mode.
Note: Backup registers will be reset only when all power has been completely removed from the chip.
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7:0
BACKUPDATA[7:0]
BACKUPDATA Data retained during Deep power-down mode.
R/W
0
4.7.2
Power Control register (PMU_CTRL)
Address Offset:
0x40
The power control register selects whether one of the ARM Cortex-M0 controlled power-down modes (Sleep mode or
Deep-sleep mode) or the Deep power-down mode is entered and provides the flags for Sleep or Deep-sleep modes
and Deep power-down modes respectively.
Note: 1. The PMU_CTRL register retains data through the Deep power-down mode when power is still
applied to the VDD pin, and will be reset only when all power has been completely removed from
the chip.
2. The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes.
Strongly recommended to set these pins as input pull-up.
Bit
Name
Description
Attribute
Reset
31:3
Reserved
R
0
2:0
MODE[2:0]
Low power mode selection
000: Disable.
001: WFI instruction will make MCU enter Deep-power down mode.
010: WFI instruction will make MCU enter Deep-sleep mode.
100: WFI instruction will make MCU enter Sleep mode.
Other: Disable
R/W
0
4.7.3
I/O Latch Control register 1 (PMU_LATCHCTRL1)
Address Offset:
0x44
