SONIX SN32F280 Series, User Manual

Page: 62 / 268

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 62
Version 1.1
Bit Name Description Attribute Reset
31:7 Reserved R 0
6:4 SYSCLKST[2:0]
System clock switch status
Set and cleared by HW to indicate which clock source is used as system
clock.
000: IHRC is used as system clock
001: ILRC is used as system clock
010: EHS X’TAL is used as system clock
011: ELS X’TAL is used as system clock
100: PLL is used as system clock
Other: Reserved
R 0
3 Reserved R 0
2:0 SYSCLKSEL[2:0]
System clock switch
Set and cleared by SW.
000: IHRC
001: ILRC
010: EHS X’TAL
011: ELS X’TAL
100: PLL output
Other: Reserved
R/W 0
3.3.5 AHB Clock Prescale register (SYS0_AHBCP)
Address Offset: 0x10
Bit Name Description Attribute Reset
31:4 Reserved R 0
3 DIV1P5
SYSCLK prescaler
0: SYSCLK = SYSCLK clock source / 1
1: SYSCLK = SYSCLK clock source / 1.5
R/W 0
2:0 AHBPRE[2:0]
AHB clock source prescaler
000: HCLK = SYSCLK / 1
001: HCLK = SYSCLK / 2
010: HCLK = SYSCLK / 4
011: HCLK = SYSCLK / 8
100: HCLK = SYSCLK / 16
101: HCLK = SYSCLK / 32
110: HCLK = SYSCLK / 64
111: HCLK = SYSCLK / 128
R/W 000b
3.3.6 System Reset Status register (SYS0_RSTST)
Address Offset: 0x14
Bit Name Description Attribute Reset
31:5
Reserved R 0
4 PORRSTF
POR reset flag
Set by HW when a POR reset occurs.
0: Read

No POR reset occurred
Write

Clear this bit
1: POR reset occurred.
R/W 1
3 EXTRSTF
External reset flag
Set by HW when a reset from the RESET pin occurs.
0: Read

No reset from RESET pin occurred
Write

Clear this bit
1: Reset from RESET pin occurred.
R/W 0
2 LVDRSTF
LVD reset flag
Set by HW when a LVD reset occurs.
0: Read

No LVD reset occurred
R/W 0