SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 182
Version 1.1
15.7.11 UART n Fractional Divider register (UARTn_FD) (n=0,1,2,3)
Address Offset: 0x28
This
register controls the clock prescaler for the baud rate generation and can be read and written at the user’s
discretion. This prescaler takes the APB clock and generates an output clock according to the specified fractional
requirements.
In most applications, the UART samples received data 16 times in each nominal bit time, and sends bits that are 16
input clocks wide. OVER8 bit allows software to control the ratio between the input clock and bit clock. This is required
for smart card mode, and provides an alternative to fractional division for other modes.
Note: If the fractional divider is active (DIVADDVAL>0) and UARTn_DLM=0, the value of the UARTn_DLL
register must
≥ 3.
Bit
Name
Description
Attribute
Reset
31:9
Reserved
R
0
8
OVER8
Oversampling value
0: Oversampling by 16
1: Oversampling by 8
R/W
0
7:4
MULVAL[3:0]
Baud rate pre-scaler multiplier value = MULVAL[3:0] +1
0000: Baud rate pre-scaler multiplier value is 1 for HW.
0001: Baud rate pre-scaler multiplier value is 2 for HW.
…
…
1111: Baud rate pre-scaler multiplier value is 16 for HW.
R/W
0
3:0
DIVADDVAL[3:0]
Baud rate generation pre-scaler divisor value. If this field is 0, fractional
baud rate generator will not impact the UART baud rate
R/W
0
15.7.12 UART n Control register (UARTn_CTRL) (n=0,1,2,3)
Address Offset: 0x30
In addition to HW flow control (Auto-CTS and Auto-RTS mechanisms), this register enables implementation of SW flow
control.
When TXEN = 1, the UART transmitter will keep sending data as long as they are available. As soon as TXEN bit
becomes 0, UART transmission will stop.
It is strongly suggested to let the UART HW implemented auto flow control features take care of limit the scope of TXEN
to SW flow control.
Note: It is advised that TXEN and RXEN are set in the same instruction if needed in order to minimize the
setup and the hold time of the receiver.
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7
TXEN
When this bit is 1, data written to the UARTn_TH register is output on the
TXD pin as soon as any preceding data has been sent.
If this bit is cleared to 0 while a character is being sent, the transmission of
that character is completed, but no further characters are sent until this bit
is set again.
R/W
1
6
RXEN
0: Disable RX related function
1: Enable RX
R/W
1
5:4
Reserved
R
0
3:1
MODE[2:0]
UARTn Mode
000: UART mode. HW will switch GPIO to UTXDn and URXDn.
R/W
0
