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SN32F260 Series

32-Bit Cortex-M0 Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 28

Version 1.5

Read



0: Interrupt disabled

1: Interrupt enabled.

2.3.2.3

IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR)

Address: 0xE000 E200 (Refer to Cortex-M0 Spec.)

The ISPR forces interrupts into the pending state, and shows the interrupts that are pending.



Note: Writing 1 to the ISPR bit corresponding to

1. an interrupt that is pending has no effect
2. a disabled interrupt sets the state of that interrupt to pending

Bit

Name

Description

Attribute

Reset

31:0

SETPEND[31:0]

Interrupt set-pending bits.
Write



0: No effect

1: Change interrupt state to pending

Read



0: Interrupt is not pending

1: Interrupt is pending

R/W

0

2.3.2.4

IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR)

Address: 0xE000 E280 (Refer to Cortex-M0 Spec.)

The ICPR removes the pending state from interrupts, and shows the interrupts that are pending.



Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.

Bit

Name

Description

Attribute

Reset

31:0

CLRPEND[31:0]

Interrupt clear-pending bits.
Write



0: No effect

1: Removes pending state of an interrupt

Read



0: Interrupt is not pending

1: Interrupt is pending

R/W

0

2.3.2.5

IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7)

Address: 0xE000 E400 + 0x4 * n (Refer to Cortex-M0 Spec.)

The interrupt priority registers provide an 8-bit priority field for each interrupt, and each register holds four priority fields.
This means the number of registers is implementation-defined, and corresponds to the number of implemented
interrupts.

Bit

Name

Description

Attribute

Reset

31:24

PRI_(4*n+3)

Each priority field holds a priority value, 0-192. The lower the value, the
greater the priority of the corresponding interrupt. The processor implements
only bits[31:30] of each field, bits [29:24] read as zero and ignore writes. This
means writing 255 to a priority register saves value 192 to the register.

R/W

0

23:16

PRI_(4*n+2)

Each priority field holds a priority value, 0-192. The lower the value, the
greater the priority of the corresponding interrupt. The processor implements
only bits[23:22] of each field, bits [21:16] read as zero and ignore writes. This
means writing 255 to a priority register saves value 192 to the register.

R/W

0

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Summary of Contents for SN32F260 Series

Page 1: ...esigned intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Bu...

Page 2: ...7 01 04 1 Modify the description of Deep Sleep Mode wakeup source 2 Add SN32F265J Package information 1 2 2017 02 13 1 Add SN32F263X Package information 1 3 2017 04 28 1 Modify typing error 1 4 2017 12 26 1 Add Note for setting the pins which are not pin out 2 Modify typing error CODE OPTION TABLE 1 5 2018 09 19 1 Modify DP DN naming rule 2 Modify typing error of CT16Bn Register ...

Page 3: ... register SYSTICK_LOAD 24 2 2 3 3 System Tick Timer Current Value register SYSTICK_VAL 25 2 2 3 4 System Tick Timer Calibration Value register SYSTICK_CALIB 25 2 3 NESTED VECTORED INTERRUPT CONTROLLER NVIC 26 2 3 1 INTERRUPT AND EXCEPTION VECTORS 26 2 3 2 NVIC REGISTERS 27 2 3 2 1 IRQ0 31 Interrupt Set Enable Register NVIC_ISER 27 2 3 2 2 IRQ0 31 Interrupt Clear Enable Register NVIC_ICER 27 2 3 2 ...

Page 4: ...TEM CONTROL REGISTERS 0 41 3 3 1 Analog Block Control register SYS0_ANBCTRL 41 3 3 2 Clock Source Status register SYS0_CSST 41 3 3 3 System Clock Configuration register SYS0_CLKCFG 41 3 3 4 AHB Clock Prescale register SYS0_AHBCP 42 3 3 5 System Reset Status register SYS0_RSTST 42 3 3 6 LVD Control register SYS0_LVDCTRL 43 3 3 7 External RESET Pin Control register SYS0_EXRSTCTRL 43 3 3 8 SWD Pin Co...

Page 5: ... 1 2 3 56 5 3 6 GPIO Port n Interrupt Event register GPIOn_IEV n 0 1 2 3 56 5 3 7 GPIO Port n Interrupt Enable register GPIOn_IE n 0 1 2 3 57 5 3 8 GPIO Port n Raw Interrupt Status register GPIOn_RIS n 0 1 2 3 57 5 3 9 GPIO Port n Interrupt Clear register GPIOn_IC n 0 1 2 3 57 5 3 10 GPIO Port n Bits Set Operation register GPIOn_BSET n 0 1 2 3 57 5 3 11 GPIO Port n Bits Clear Operation register GP...

Page 6: ...al Match Control register 2 CT16Bn_EMC2 n 1 74 6 7 17 CT16Bn PWM Control register CT16Bn_PWMCTRL n 1 75 6 7 18 CT16Bn PWM Control register 2 CT16Bn_PWMCTRL2 n 1 77 6 7 19 CT16Bn PWM Enable register CT16Bn_PWMENB n 1 78 6 7 20 PWM IO Enable register CT16Bn_PWMIOENB n 1 79 6 7 21 CT16Bn Timer Raw Interrupt Status register CT16Bn_RIS n 0 1 81 6 7 22 CT16Bn Timer Interrupt Clear register CT16Bn_IC n 0...

Page 7: ...MODE 98 9 5 3 ARBITRATION 98 9 6 I2C SLAVE MODES 99 9 6 1 SLAVE TRANSMITTER MODE 99 9 6 2 SLAVE RECEIVER MODE 99 9 7 I2C REGISTERS 100 9 7 1 I2C n Control register I2Cn_CTRL n 0 100 9 7 2 I2C n Status register I2Cn_STAT n 0 101 9 7 3 I2C n TX Data register I2Cn_TXDATA n 0 102 9 7 4 I2C n RX Data register I2Cn_RXDATA n 0 102 9 7 5 I2C n Slave Address 0 register I2Cn_SLVADDR0 n 0 102 9 7 6 I2C n Sla...

Page 8: ...SB_FRMNO 114 10 9 12 USB PHY Parameter Register USB_PHYPRM 114 10 9 13 USB PHY Parameter Register 2 USB_PHYPRM2 115 10 9 14 USB PHY Parameter Register USB_PS2CTL 115 10 9 15 USB Read Write Address Register USB_RWADDR 115 10 9 16 USB Read Write Data Register USB_RWDATA 116 10 9 17 USB Read Write Status Register USB_RWSTATUS 116 10 9 18 USB Read Write Address Register2 USB_RWADDR2 116 10 9 19 USB Re...

Page 9: ... 12 4 DEBUG NOTE 124 12 4 1 LIMITATIONS 124 12 4 2 DEBUG RECOVERY 124 12 4 3 INTERNAL PULL UP DOWN RESITIORS on SWD PINS 125 1 1 13 3 3 DEVELOPMENT TOOL 126 13 1 SN LINK V3 0 127 13 2 SN32F268 STARTER KIT 128 1 1 14 4 4 ELECTRICAL CHARACTERISTIC 129 14 1 ABSOLUTE MAXIMUM RATING 129 14 2 ELECTRICAL CHARACTERISTIC 129 1 1 15 5 5 FLASH ROM PROGRAMMING PIN 130 1 1 16 6 6 PACKAGE INFORMATION 131 16 1 L...

Page 10: ...rogrammable WatchDog Timer WDT Operating modes Programmable watchdog frequency with watchdog Normal Sleep and Deep sleep clock source and divider Fcpu Instruction cycle System tick timer FCPU FHCLK FSYSCLK 1 FSYSCLK 2 FSYSCLK 4 24 bit timer FSYSCLK 128 The system tick timer clock is fixed to the frequency of the system clock In System Progamming ISP supported The SysTick timer is intended to gener...

Page 11: ...M GPIO with Wakeup Package SN32F268F 32KB 2KB 48 MHz 16 bitx2 1 1 22 CH 42 LQFP48 SN32F267J 32KB 2KB 48 MHz 16 bitx2 1 1 22 CH 40 QFN46 SN32F265J 32KB 2KB 48 MHz 16 bitx2 1 1 17 CH 26 QFN33 SN32F2641J 32KB 2KB 48 MHz 16 bitx2 1 1 13 CH 22 QFN28 SN32F264S X 32KB 2KB 48 MHz 16 bitx2 1 1 11 CH 22 SOP28 SSOP28 SN32F263X 32KB 2KB 48 MHz 16 bitx2 1 1 11 CH 18 SSOP24 ...

Page 12: ...LKOUT CT16B1_PWM 22 21 CT16B1_PWM 19 0 SCK0 SDI0 SDO0 RESET ARM CORTEX M0 CLOCK GENERATION EEPROM 32KB SRAM 2KB SYS POWER CONTROL SYSTEM FUNCTIONS POWER REGULATOR 1 ILRC 32KHz IHRC 48MHz LVD Clocks Controls AHB LITE BUS AHB TO APB BRIDGE APB BUS GPIO USB VCORE VDD 2 5V 5 5V WDT D D CT16B0_CAP0 POWER REGULATOR 2 VREG33 VBUS 4 0 5 5V PMU 16 bit TIMER 0 16 bit TIMER 1 with 22 PWM SPI0 SCL SDA I2C ...

Page 13: ...HCLK and System Timer to SYS and to PMU AHB clock for GPIOn GPIOnCLKEN n 0 1 2 3 GPIOn block AHB Prescaler 1 2 4 128 SPIn_PCLK AHB clock for SPIn SPInCLKEN n 0 SPIn register block SPIn clock source CT16Bn_PCLK AHB clock for CT16Bn CT16BnCLKEN n 0 1 CT16Bn register block CT16Bn clock source AHB clock for SRAM SRAM block AHB clock for FLASH FLASH block CLKOUT Prescaler 1 2 4 128 WDTCLKEN HCLK HCLK I...

Page 14: ...KOUT 4 33 P2 7 P0 1 CT16B1_PWM1 5 32 P2 6 P0 2 CT16B1_PWM2 6 SN32F268F 31 P2 5 P0 3 CT16B1_PWM3 7 30 P2 4 P0 4 CT16B1_PWM4 SCL0 8 29 P2 3 P0 5 CT16B1_PWM5 SDA0 9 28 P3 8 RESET CT16B1_PWM22 P0 6 CT16B1_PWM6 10 27 P3 7 SWDIO P0 7 CT16B1_PWM7 11 26 P3 6 SWCLK P0 8 CT16B1_PWM8 12 25 P3 5 CT16B1_PWM21 13 14 15 16 17 18 19 20 21 22 23 24 P0 9 CT16B1_PWM9 P0 10 CT16B1_PWM10 P0 11 CT16B1_PWM11 P0 12 CT16B...

Page 15: ... CT16B1_PWM3 6 27 P3 8 RESET CT16B1_PWM22 P0 4 CT16B1_PWM4 SCL0 7 26 P3 7 SWDIO P0 5 CT16B1_PWM5 SDA0 8 25 P3 6 SWCLK P0 6 CT16B1_PWM6 9 24 P3 5 CT16B1_PWM21 10 11 12 13 14 15 16 17 18 19 20 21 22 23 P0 7 CT16B1_PWM7 P0 8 CT16B1_PWM8 P0 9 CT16B1_PWM9 P0 10 CT16B1_PWM10 P0 11 CT16B1_PWM11 P0 12 CT16B1_PWM12 P0 13 CT16B1_PWM13 P0 14 CT16B1_PWM14 P0 15 CT16B1_PWM15 P3 0 CT16B1_PWM16 P3 1 CT16B1_PWM17...

Page 16: ...LKOUT 4 21 P3 6 SWCLK P0 1 CT16B1_PWM1 5 20 P3 5 CT16B1_PWM21 P0 2 CT16B1_PWM2 6 19 P3 4 P0 3 CT16B1_PWM3 7 18 P3 3 CT16B1_PWM19 P0 4 CT16B1_PWM4 SCL0 8 33 VSS 17 P3 2 CT16B1_PWM18 9 10 11 12 13 14 15 16 P0 5 CT16B1_PWM5 SDA0 P0 10 CT16B1_PWM10 P0 11 CT16B1_PWM11 P0 12 CT16B1_PWM12 P0 13 CT16B1_PWM13 P0 14 CT16B1_PWM14 P0 15 CT16B1_PWM15 P3 1 CT16B1_PWM17 Note The pins which are not pin out shall ...

Page 17: ...IO P0 1 CT16B1_PWM1 4 SN32F2641J 18 P3 6 SWCLK P0 2 CT16B1_PWM2 5 17 P3 5 CT16B1_PWM21 P0 3 CT16B1_PWM3 6 16 P3 4 P0 4 CT16B1_PWM4 SCL0 7 15 P3 3 CT16B1_PWM19 8 9 10 11 12 13 14 P0 5 CT16B1_PWM5 SDA0 P0 10 CT16B1_PWM10 P0 11 CT16B1_PWM11 P0 12 CT16B1_PWM12 P0 13 CT16B1_PWM13 P0 14 CT16B1_PWM14 P0 15 CT16B1_PWM15 Note The pins which are not pin out shall be set correctly to decrease power consumpti...

Page 18: ...CT16B1_PWM12 SN32F264S X Note The pins which are not pin out shall be set correctly to decrease power consumption in low power modes Strongly recommended to set these pins as input pull up SN32F263X SSOP 24pins VDD 1 U 24 VDDIO1 VREG33 2 23 P1 1 CT16B0_CAP0 D PSCLK 3 22 P1 2 SEL0 D PSDATA 4 21 P1 3 SCK0 P0 0 CT16B1_PWM0 CLKOUT 5 20 P1 4 MISO0 P0 1 CT16B1_PWM1 6 19 P1 5 MOSI0 P0 2 CT16B1_PWM2 7 18 ...

Page 19: ...eneral purpose digital input output pin O CT16B1_PWM2 PWM output 2 for CT16B1 P0 3 CT16B1_PWM3 I O P0 3 General purpose digital input output pin O CT16B1_PWM3 PWM output 3 for CT16B1 P0 4 CT16B1_PWM4 SCL0 I O P0 4 General purpose digital input output pin I O CT16B1_PWM4 PWM output 4 for CT16B1 I O SCL0 I2C clock input output P0 5 CT16B1_PWM5 SDA0 I O P0 5 General purpose digital input output pin I...

Page 20: ... 19 for CT16B1 P3 4 I O P3 4 General purpose digital input output pin P3 5 CT16B1_PWM2 1 I O P3 5 General purpose digital input output pin O CT16B1_PWM21 PWM output 21 for CT16B1 P3 6 SWCLK I O P3 6 General purpose digital input output pin I SWCLK Serial Wire Clock pin P3 7 SWDIO I O P3 7 General purpose digital input output pin I O SWDIO Serial Wire Data input output pin P3 8 RESET CT16B1 _PWM22 ...

Page 21: ...t Bus GPIOPn_MODE RPD GPIOn_CFG GPIOPn_MODE Specific Input Bus Specific Input Function Control Bit Specific Output Function Control Bit Some specific functions switch I O direction directly not through GPIOn_MODE register Bi direction I O Pin Shared with Specific Digital Output Function e g SPI I2C RPU Output Latch Pin GPIOn_CFG I O Input Bus Output Bus GPIOPn_MODE RPD GPIOn_CFG GPIOPn_MODE Specif...

Page 22: ... 0x4001 4000 WDT 0x4001 6000 0x4001 8000 0x4001 C000 USB Reserved 0x4002 8000 0x4002 6000 Reserved Reserved I2C0 0x4004 4000 0x4004 6000 0x4004 8000 GPIO 2 GPIO 3 GPIO 0 GPIO 1 Reserved 0x4008 0000 0xE000 0000 0xE010 0000 0xE000 ED00 0xE000 F000 Reserved NVIC Debug Control 0xE000 E000 Reserved SPI0 Reserved SYS0 Reserved 0x4006 0000 FMC Reserved CT16B0 CT16B1 Reserved Reserved Reserved PMU 0x4006 ...

Page 23: ...a fixed 10 ms time interval between interrupts The system tick timer is enabled through the SysTick control register The system tick timer clock is fixed to the frequency of the system clock The block diagram of the SysTick timer SYSTICK_CALIB SysTick interrupt SYSTICK_LOAD SYSTICK_VAL 24 bit down counter CLKSOURCE System Clock Ref clock Fix to 1 1 0 SYSTICK_CTRL clock Load data Private Peripheral...

Page 24: ...SOURCE Selects the SysTick timer clock source 0 reference clock 1 system clock Fixed R 1 1 TICKINT System Tick interrupt enable 0 Disable the System Tick interrupt 1 Enable the System Tick interrupt the interrupt is generated when the System Tick counter counts down to 0 R W 0 0 ENABLE System Tick counter enable 0 Disable 1 Enable R W 0 2 2 3 2 System Tick Timer Reload value register SYSTICK_LOAD ...

Page 25: ... W 0x7E7F35 2 2 3 4 System Tick Timer Calibration Value register SYSTICK_CALIB Address 0xE000 E01C Refer to Cortex M0 Spec Bit Name Description Attribute Reset 31 NOREF Indicates the reference clock to M0 is provided or not 1 No reference clock provided R 1 30 SKEW Indicates whether the TENMS value is exact an inexact TENMS value can affect the suitability of SysTick as a software real time clock ...

Page 26: ...n Address Offset 0 Reserved 0x0000 0000 1 3 Reset Reset 0x0000 0004 2 2 NMI_Handler Non maskable interrupt 0x0000 0008 3 1 HardFault_Handler All class of fault 0x0000 000C 4 10 Reserved Reserved Reserved 11 Settable SVCCalll 0x0000 002C 12 13 Reserved Reserved Reserved 14 Settable PendSV 0x0000 0038 15 Settable SysTick 0x0000 003C 16 Settable IRQ0 NDTIRQ NDT 0x0000 0040 17 Settable IRQ1 USBIRQ USB...

Page 27: ...IRQ GPIO interrupt status of port 2 0x0000 00B4 46 Settable IRQ30 P1IRQ GPIO interrupt status of port 1 0x0000 00B8 47 Settable IRQ31 P0IRQ GPIO interrupt status of port 0 0x0000 00BC 2 3 2 NVIC REGISTERS 2 3 2 1 IRQ0 31 Interrupt Set Enable Register NVIC_ISER Address 0xE000 E100 Refer to Cortex M0 Spec The ISER enables interrupts and shows the interrupts that are enabled Bit Name Description Attr...

Page 28: ... Reset 31 0 CLRPEND 31 0 Interrupt clear pending bits Write 0 No effect 1 Removes pending state of an interrupt Read 0 Interrupt is not pending 1 Interrupt is pending R W 0 2 3 2 5 IRQ0 31 Interrupt Priority Register NVIC_IPRn n 0 7 Address 0xE000 E400 0x4 n Refer to Cortex M0 Spec The interrupt priority registers provide an 8 bit priority field for each interrupt and each register holds four prio...

Page 29: ... saves value 192 to the register R W 0 2 4 APPLICATION INTERRUPT AND RESET CONTROL AIRC Address 0xE000 ED0C Refer to Cortex M0 Spec The entire MCU including the core can be reset by SW by setting the SYSRESREQ bit in the AIRC register in Cortex M0 spec Note To write to this register user must write 0x05FA to the VECTKEY field at the same time otherwise the processor ignores the write Bit Name Desc...

Page 30: ...ller SONiX TECHNOLOGY CO LTD Page 30 Version 1 5 2 5CODE OPTION TABLE Address 0x1FFF 2000 Bit Name Description Attribute Reset 31 16 Code Security 15 0 Code Security 0x0000 CS0 0x5A5A CS1 0xA5A5 CS2 Other CS2 R W 0000 15 0 Reserved R All 0 Bit 1 1 ...

Page 31: ...ister LR It stores the return information for subroutines function calls and exceptions PC R15 The Program Counter PC It contains the current program address On reset the processor loads the PC with the value of the reset vector at address 0x00000004 PSR The Program Status Register PSR combines Application Program Status Register APSR Interrupt Program Status Register IPSR Execution Program Status...

Page 32: ...nder client terminal application users have to take care of the power on reset time for the master terminal requirement The reset timing diagram is as following VDD VSS VDD VSS Watchdog Normal Run Watchdog Stop System Normal Run System Stop LVD Detect Level External Reset Low Detect External Reset High Detect Watchdog Overflow Watchdog Reset Delay Time External Reset Delay Time Power On Delay Time...

Page 33: ...can improve main routine fail Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Note Please refer to the WATCHDOG TIMER about watchdog timer detail information 3 1 3 BROWN OUT RESET 3 1 3 1 BROWN OUT DESCRIPTION The brown out reset is a power dropping condition The power drops from normal voltage to low voltage ...

Page 34: ...ON To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level Different system executing rates have different system minimum operating voltage The electrical characteristic section shows the system voltage to executing rate relationship Vdd V System Rate Fcpu System Mini Operating Voltage System Reset Voltage Dead ...

Page 35: ...ce This method also can improve brown out reset condition and make sure the system to return normal mode If the system reset by watchdog and the power is still in dead band the system reset sequence won t be successful and the system stays in reset status until the power return to normal range Reduce the system executing rate If the system rate is fast and the dead band exists to reduce the system...

Page 36: ...l power condition e g brown out reset in AC power application 3 1 4 1 SIMPLY RC RESET CIRCUIT MCU VDD VSS VCC GND RST R1 47K ohm C1 0 1uF R2 100 ohm This is the basic reset circuit and only includes R1 and C1 The RC circuit operation makes a slow rising signal into reset pin as power up The reset signal is slower than VDD power up timing and system occurs a power on signal from the timing differen...

Page 37: ...S 3 1 4 3 ZENER DIODE RESET CIRCUIT MCU VDD VSS VCC GND RST R1 33K ohm R3 40K ohm R2 10K ohm Vz Q1 E C B The Zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely Use Zener voltage to be the active level When VDD voltage level is above Vz 0 7V the C terminal of the PNP transistor outputs high voltage and MCU operates normally When VDD is be...

Page 38: ...e system power consumption Note Under unstable power condition as brown out reset Zener diode reset circuit and Voltage bias reset circuit can protects system no any error occurrence as power dropping When power drops below the reset detect voltage the system reset would be triggered and then system executes reset sequence That makes sure the system work well under unstable power situation 3 1 4 5...

Page 39: ...clock is generated from on chip low speed RC oscillator circuit ILRC 32KHz 3 2 1 INTERNAL RC CLOCK SOURCE 3 2 1 1 Internal High speed RC Oscillator IHRC The internal high speed oscillator is 48MHz RC type The accuracy is 0 2 under commercial condition The IHRC can be switched on and off using the IHRCEN bit in Analog Block Control register SYS0_ANBCTRL 3 2 1 2 Internal Low speed RC Oscillator ILRC...

Page 40: ...t yet ready is selected the switch will occur when the clock source is ready Ready bits in SYS0_CSST register indicate which clock s is are ready and SYSCLKST bits in SYS0_CLKCFG register indicate which clock is currently used as system clock 3 2 3 CLOCK OUT CAPABITITY The MCU clock output CLKOUT capability allows the clock to be output onto the external CLKOUT pin The configuration registers of t...

Page 41: ...sable internal 48 MHz RC oscillator 1 Enable internal 48 MHz RC oscillator R W 1 3 3 2 Clock Source Status register SYS0_CSST Address Offset 0x08 Bit Name Description Attribute Reset 31 1 Reserved R 0 0 IHRCRDY IHRC ready flag After the IHRCEN bit is cleared IHRCRDY is cleared by HW after 6 IHRC clock cycles 0 IHRC not ready 1 IHRC ready R 1 3 3 3 System Clock Configuration register SYS0_CLKCFG Ad...

Page 42: ...served R 0 4 PORRSTF POR reset flag Set by HW when a POR reset occurs 0 Read No POR reset occurred Write Clear this bit 1 POR reset occurred R W 1 3 EXTRSTF External reset flag Set by HW when a reset from the RESET pin occurs 0 Read No reset from RESET pin occurred Write Clear this bit 1 Reset from RESET pin occurred R W 0 2 LVDRSTF LVD reset flag Set by HW when a LVD reset occurs 0 Read No LVD re...

Page 43: ... LVD interrupt level 01 2 40V 10 3 30V Other Reserved R W 10b 4 3 Reserved R 0 2 0 LVDRSTLVL 2 0 LVD reset level 010 2 40V 100 3 30V Other Reserved R W 010b 3 3 7 External RESET Pin Control register SYS0_EXRSTCTRL Address Offset 0x1C Bit Name Description Attribute Reset 31 1 Reserved R 0 0 RESETDIS External RESET pin disable bit 0 Enable external RESET pin P3 8 acts as RESET pin 1 Disable P3 8 act...

Page 44: ...o SRAM 00 11 Reserved R W 01b 3 3 10 Noise Detect Control register SYS0_NDTCTRL Address Offset 0x28 Bit Name Description Attribute Reset 31 2 Reserved R 0 1 NDT5V_IE NDT0 Disablefor VDD 5V interrupt enable bit 0 Disable 1 Enable The noise on IC VDD 5V domain detected by NDT5V IP will trigger NDT interrupt IRQ0 R W 0 0 Reserved R 0 3 3 11 Noise Detect Status register SYS0_NDTSTS Address Offset 0x2C...

Page 45: ...ies 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 45 Version 1 5 Bit Name Description Attribute Reset 31 3 Reserved R 0 2 0 AEFT 2 0 HW anti EFT ability 000 No 010 Low 011 Medium 100 Strong R W 000 ...

Page 46: ...8 CLKOUTSEL 2 0 Clock output source 000 Disable 001 ILRC clock 100 HCLK 101 IHRC clock Others Reserved R W 0 27 25 Reserved R 0 24 WDTCLKEN Enables clock for WDT 0 Disable 1 Enable R W 1 23 22 Reserved R 0 21 I2C0LKEN Enables clock for I2C0 0 Disable 1 Enable R W 0 20 13 Reserved R 0 12 SPI0CLKEN Enables clock for SPI0 0 Disable 1 Enable R W 0 11 8 Reserved R 0 7 CT16B1CLKEN Enables clock for CT16...

Page 47: ...ource 1 001 Clock out source 2 010 Clock out source 4 011 Clock out source 8 100 Clock out source 16 101 Clock out source 32 110 Clock out source 64 111 Clock out source 128 Other Reserved R W 0 27 23 Reserved R 0 22 20 WDTPRE 2 0 WDT clock source prescaler 000 WDT_PCLK WDT clock source 1 001 WDT_PCLK WDT clock source 2 010 WDT_PCLK WDT clock source 4 011 WDT_PCLK WDT clock source 8 100 WDT_PCLK W...

Page 48: ...m clock divider value This allows a trade off of power versus processing speed based on application requirements Run time power control allows disable the clocks to individual on chip peripherals allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application Selected peripherals have their own clock divider for power cont...

Page 49: ...us at the VDD 3 3V The RESET pin has keep functionality in Deep sleep mode The Deep sleep mode is entered by using the following steps 1 Write 2 to PMU_CTRL register 2 Execute ARM WFI instruction The advantage of the Deep sleep mode is that can power down clock generating blocks such as oscillators thereby gaining far greater dynamic power savings over Sleep mode In addition the Flash can be power...

Page 50: ...e IHRC wakeup time is as the following The total Wakeup time of IHRC 10us Example FIHRC 48MHz the wakeup time is as the following The total Wakeup time 10us FIHRC 48MHz Note The high clock start up time is depended on the VDD and oscillator type of high clock 4 5STATE MACHINE OF PMU Reset Run mode Deep sleep mode Sleep mode Wake up condition Interrupt Wake up condition GPIO0 1 Reset condition One ...

Page 51: ...FW Disable HW Disable ILRC HW Enable HW Enable HW Enable HW Disable Cortex M0 Running Stop Stop Stop Flash ROM Enable Standby Standby Standby Enable Standby Data RAM Enable Standby Standby Standby Standby 3 level LVD By LVDEN By LVDEN By LVDEN USB By USBEN By USBEN Disable Peripherals By Enable bit of each peripherals Disable HCLK IO status Output Low Output Low Output Low Wakeup Source N A All in...

Page 52: ...trol register selects whether one of the ARM Cortex M0 controlled power down modes Sleep mode or Deep sleep mode is entered and provides the flags for Sleep or Deep sleep modes respectively Bit Name Description Attribute Reset 31 3 Reserved R 0 2 0 MODE 2 0 Low power mode selection 010 WFI instruction will make MCU enter Deep sleep mode 100 WFI instruction will make MCU enter Sleep mode Other Disa...

Page 53: ...dges and on both edges Individual interrupt levels can be programmed Internal pull up resistor All GPIO pins are inputs and floating by default 5 2GPIO MODE The MODE bits in the GPIOn_CFG n 0 1 2 3 register allow the selection of on chip pull up resistors for each pin or select the inactive mode or inactive with Schmitt trigger disabled mode The possible on chip resistor configurations are pull up...

Page 54: ...me Description Attribute Reset 31 16 CURRENT 15 0 Driving Sinking current selection x 0 to 15 0 Typical 10mA 1 Typical 20mA R W 0 15 0 MODE 15 0 Selects pin x as input or output x 0 to 15 0 Pn x is configured as input 1 Pn x is configured as output R W 0 5 3 3 GPIO Port n Configuration register GPIOn_CFG n 0 1 2 3 Address offset 0x08 Reset value n 0 0xAAAA AAAA n 1 0x0000 0AAA n 2 0x002A AAAA n 3 ...

Page 55: ...gger disabled Data register keep low R W 10b 19 18 CFG9 1 0 Configuration of Pn 9 00 Pull up resistor enabled 01 Reserved 10 Inactive no pull up resistor enabled Schmitt trigger enabled 11 Inactive no pull up resistor enabled Schmitt trigger disabled Data register keep low R W 10b 17 16 CFG8 1 0 Configuration of Pn 8 00 Pull up resistor enabled 01 Reserved 10 Inactive no pull up resistor enabled S...

Page 56: ...nabled Schmitt trigger enabled 11 Inactive no pull up resistor enabled Schmitt trigger disabled Data register keep low R W 10b 5 3 4 GPIO Port n Interrupt Sense register GPIOn_IS n 0 1 2 3 Address offset 0x0C Bit Name Description Attribute Reset 31 16 Reserved R 0 15 0 IS 15 0 Selects interrupt on pin x as level or edge sensitive x 0 to 15 0 Interrupt on Pn x is configured as edge sensitive 1 Inte...

Page 57: ... GPIO control raw interrupts A GPIO interrupt is sent to the interrupt controller if the corresponding bit in GPIOn_IE register is set Bit Name Description Attribute Reset 31 16 Reserved R 0 15 0 IF 15 0 GPIO raw interrupt flag x 0 to 15 0 No interrupt on Pn x 1 Interrupt requirements met on Pn x R 0 5 3 9 GPIO Port n Interrupt Clear register GPIOn_IC n 0 1 2 3 Address offset 0x20 Bit Name Descrip...

Page 58: ...GPIOn_BCLR n 0 1 2 3 Address offset 0x28 In order for SW to clear GPIO bits without affecting any other pins in a single write operation the GPIO bit is cleared if the corresponding bit in this register is set Bit Name Description Attribute Reset 31 16 Reserved R 0 15 0 BCLR 15 0 Bit clear enable x 0 to 15 0 No effect on Pn x 1 Clear Pn x W 0 ...

Page 59: ... 16 bit capture channels that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt The timer and prescaler may be configured to be cleared on a designated capture event This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailin...

Page 60: ...age 60 Version 1 5 6 4 BLOCK DIAGRAM CT16Bn_PWMx STOP MRx MRxIF MRxIE PCLK CEN PC PRE TC CEN MRx Interrupt MRxSTOP STOP CRST CRST RESET RESET MRxRST CAP0 CAP0EN CAP0FE CAP0RE CAP0IE CAP0 Interrupt CT16Bn_CAP0 PWMxEN PWMxIOEN EMCx PWMxMODE PWMxNIOEN PWMxNDB CT16Bn_PWMxN CAP0IE ...

Page 61: ...ll length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value PCLK CT16Bn_PC CT16Bn_TC TC Reset Interrupt 2 0 1 2 0 1 2 0 4 5 6 0 The following figure shows a timer configured to stop and generate an interrupt on match The CT16Bn_PRE register is set to 2 and the CT16Bn_MRx register is set to 6 In the next cl...

Page 62: ...PWM cycle 4 If a match register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length 5 If a match register is set to zero then the PWM output will go to HIGH the first time the timer go...

Page 63: ...WM cycle 4 If a match register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to HIGH on the next clock tick Therefore the PWM output will always consist of a one clock tick wide low pulse with a period determined by the PWM cycle length 5 If a match register is set to zero then the PWM output will go LOW the first time the timer goes back t...

Page 64: ...ishes R W 0 0 CEN Counter Enable 0 Disable Counter 1 Enable Timer Counter and Prescale Counter for counting CEN bit shall be set at last Always Edge aligned Up counting mode R W 0 6 7 2 CT16Bn Timer Counter register CT16Bn_TC n 0 1 Address Offset 0x04 The 16 bit Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the ...

Page 65: ... edge falling edge either of edges or no changes in the level of the selected CAP input Only if the identified event occurs and the event corresponds to the one selected by CTM bits in this register will the Timer Counter register be incremented Effective processing of the externally supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to ...

Page 66: ...atches TC 0 Disable 1 Enable R W 0 28 MR9RST Enable reset TC when MR9 matches TC 0 Disable 1 Enable R W 0 27 MR9IE Enable generating an interrupt based on CM 2 0 when MR9 matches the value in the TC 0 Disable 1 Enable R W 0 26 MR8STOP Stop MR8 TC and PC will stop and CEN bit will be cleared if MR8 matches TC 0 Disable 1 Enable R W 0 25 MR8RST Enable reset TC when MR8 matches TC 0 Disable 1 Enable ...

Page 67: ... the value in the TC 0 Disable 1 Enable R W 0 11 MR3STOP Stop MR3 TC and PC will stop and CEN bit will be cleared if MR3 matches TC 0 Disable 1 Enable R W 0 10 MR3RST Enable reset TC when MR3 matches TC 0 Disable 1 Enable R W 0 9 MR3IE Enable generating an interrupt based on CM 2 0 when MR3 matches the value in the TC 0 Disable 1 Enable R W 0 8 MR2STOP Stop MR2 TC and PC will stop and CEN bit will...

Page 68: ...ll be cleared if MR18 matches TC 0 Disable 1 Enable R W 0 25 MR18RST Enable reset TC when MR18 matches TC 0 Disable 1 Enable R W 0 24 MR18IE Enable generating an interrupt based on CM 2 0 when MR18 matches the value in the TC 0 Disable 1 Enable R W 0 23 MR17STOP Stop MR17 TC and PC will stop and CEN bit will be cleared if MR17 matches TC 0 Disable 1 Enable R W 0 22 MR17RST Enable reset TC when MR1...

Page 69: ...ng an interrupt based on CM 2 0 when MR13 matches the value in the TC 0 Disable 1 Enable R W 0 8 MR12STOP Stop MR12 TC and PC will stop and CEN bit will be cleared if MR12 matches TC 0 Disable 1 Enable R W 0 7 MR12RST Enable reset TC when MR12 matches TC 0 Disable 1 Enable R W 0 6 MR12IE Enable generating an interrupt based on CM 2 0 when MR12 matches the value in the TC 0 Disable 1 Enable R W 0 5...

Page 70: ...3 matches the value in the TC 0 Disable 1 Enable R W 0 8 MR22STOP Stop MR22 TC and PC will stop and CEN bit will be cleared if MR22 matches TC 0 Disable 1 Enable R W 0 7 MR22RST Enable reset TC when MR22 matches TC 0 Disable 1 Enable R W 0 6 MR22IE Enable generating an interrupt based on CM 2 0 when MR22 matches the value in the TC 0 Disable 1 Enable R W 0 5 MR21STOP Stop MR21 TC and PC will stop ...

Page 71: ...rate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the CT16Bn_MCTRL register Bit Name Description Attribute Reset 31 16 Reserved R 0 15 0 MR 15 0 Timer counter match value R W 0 6 7 12 CT16Bn Capture Control register CT16Bn_CAPCTRL n 0 Address Offset 0x80 The Capture Control register is used to control whether the Capture register is loaded with t...

Page 72: ...en the TC and MR18 are equal this bit will act according to EMC18 bits and also drive the state of CT16Bn_PWM18 output R W 0 17 EM17 When the TC and MR17 are equal this bit will act according to EMC17 bits and also drive the state of CT16Bn_PWM17 output R W 0 16 EM16 When the TC and MR16 are equal this bit will act according to EMC16 bits and also drive the state of CT16Bn_PWM16 output R W 0 15 EM...

Page 73: ...30 EMC15 1 0 Determines the functionality of CT16Bn_PWM15 00 Do Nothing 01 CT16Bn_PWM15 pin is LOW 10 CT16Bn_PWM15 pin is HIGH 11 Toggle CT16Bn_PWM15 pin R W 0 29 28 EMC14 1 0 Determines the functionality of CT16Bn_PWM14 00 Do Nothing 01 CT16Bn_PWM14 pin is LOW 10 CT16Bn_PWM14 pin is HIGH 11 Toggle CT16Bn_PWM14 pin R W 0 27 26 EMC13 1 0 Determines the functionality of CT16Bn_PWM13 00 Do Nothing 01...

Page 74: ...1 1 0 Determines the functionality of CT16Bn_PWM1 00 Do Nothing 01 CT16Bn_PWM1 pin is LOW 10 CT16Bn_PWM1 pin is HIGH 11 Toggle CT16Bn_PWM1 R W 0 1 0 EMC0 1 0 Determines the functionality of CT16Bn_PWM0 00 Do Nothing 01 CT16Bn_PWM0 pin is LOW 10 CT16Bn_PWM0 pin is HIGH 11 Toggle CT16Bn_PWM0 R W 0 6 7 16 CT16Bn External Match Control register 2 CT16Bn_EMC2 n 1 Address Offset 0x90 The External Match ...

Page 75: ...s in any of the other match registers the PWM output is set to HIGH The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared Bit Name Description Attribute Reset 31 30 PWM15MODE 1 0 PWM15 output 00 PWM mode 1 PWM15 is 0 when TC MR15 during Up counting period 01 PWM ...

Page 76: ...uring Up counting period 10 PWM7 is forced to 0 11 PWM7 is forced to 1 R W 0 13 12 PWM6MODE 1 0 PWM6 output 00 PWM mode 1 PWM6 is 0 when TC MR6 during Up counting period 01 PWM mode 2 PWM6 is 1 when TC MR6 during Up counting period 10 PWM6 is forced to 0 11 PWM6 is forced to 1 R W 0 11 10 PWM5MODE 1 0 PWM5 output 00 PWM mode 1 PWM5 is 0 when TC MR5 during Up counting period 01 PWM mode 2 PWM5 is 1...

Page 77: ... The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared Bit Name Description Attribute Reset 31 14 Reserved R 0 13 12 PWM22MODE 1 0 PWM22 output 00 PWM mode 1 PWM22 is 0 when TC MR22 during Up counting period 01 PWM mode 2 PWM22 is 1 when TC MR22 during Up countin...

Page 78: ...currently HIGH match outputs configured as PWM outputs are cleared Bit Name Description Attribute Reset 31 23 Reserved R 0 22 PWM22EN PWM22 enable 0 CT16Bn_PWM22 is controlled by EM22 1 PWM mode is enabled for CT16Bn_PWM22 R W 0 21 PWM21EN PWM21 enable 0 CT16Bn_PWM21 is controlled by EM21 1 PWM mode is enabled for CT16Bn_PWM21 R W 0 20 Reserved R 0 19 PWM19EN PWM19 enable 0 CT16Bn_PWM19 is control...

Page 79: ...EM0 1 PWM mode is enabled for CT16Bn_PWM0 R W 0 6 7 20 PWM IO Enable register CT16Bn_PWMIOENB n 1 Address Offset 0xA0 The PWM Control register is used to configure the match outputs as PWM outputs Each match output can be independently set to perform either as PWM output or as match output whose function is controlled by CT16Bn_EM register For each timer a maximum of 4 single edge controlled PWM o...

Page 80: ...act as GPIO 1 CT16Bn_PWM11 pin act as match output and output signal depends on PWM11EN bit R W 0 10 PWM10IOEN CT16Bn_PWM10 GPIO selection bit 0 CT16Bn_PWM10 pin act as GPIO 1 CT16Bn_PWM10 pin act as match output and output signal depends on PWM10EN bit R W 0 9 PWM9IOEN CT16Bn_PWM9 GPIO selection bit 0 CT16Bn_PWM9 pin act as GPIO 1 CT16Bn_PWM9 pin act as match output and output signal depends on P...

Page 81: ...Interrupt requirements met on match channel 21 R 0 20 Reserved R 0 19 MR19IF Interrupt flag for match channel 19 0 No interrupt on match channel 19 1 Interrupt requirements met on match channel 19 R 0 18 MR18IF Interrupt flag for match channel 18 0 No interrupt on match channel 18 1 Interrupt requirements met on match channel 18 R 0 17 MR17IF Interrupt flag for match channel 17 0 No interrupt on m...

Page 82: ...errupt requirements met on match channel 3 R 0 2 MR2IF Interrupt flag for match channel 2 0 No interrupt on match channel 2 1 Interrupt requirements met on match channel 2 R 0 1 MR1IF Interrupt flag for match channel 1 0 No interrupt on match channel 1 1 Interrupt requirements met on match channel 1 R 0 1 MR0IF Interrupt flag for match channel 0 0 No interrupt on match channel 0 1 Interrupt requir...

Page 83: ...9IF bit W 0 8 MR8IC 0 No effect 1 Clear MR8IF bit W 0 7 MR7IC 0 No effect 1 Clear MR7IF bit W 0 6 MR6IC 0 No effect 1 Clear MR6IF bit W 0 5 MR5IC 0 No effect 1 Clear MR5IF bit W 0 4 MR4IC 0 No effect 1 Clear MR4IF bit W 0 3 MR3IC 0 No effect 1 Clear MR3IF bit W 0 2 MR2IC 0 No effect 1 Clear MR2IF bit W 0 1 MR1IC 0 No effect 1 Clear MR1IF bit W 0 0 MR0IC 0 No effect 1 Clear MR0IF bit W 0 ...

Page 84: ... the Watchdog and setup the Watchdog timer operating mode in WDT_CFG register 5 The Watchdog should be fed again by writing 0x55AA to WDT_FEED register before the Watchdog counter underflows to prevent reset or interrupt When the watchdog is started by setting the WDTEN in WDT_CFG register the time constant value is loaded in the watchdog counter and the counter starts counting down When the Watch...

Page 85: ...cro Controller SONiX TECHNOLOGY CO LTD Page 85 Version 1 5 7 2 BLOCK DIAGRAM WDT_FEED WDT_TC 128 8 bit Down Counter WDINT WDTIE WDTEN WDT_PCLK Feed OK Feed Watchdog Enable Counter Reload Counter underflow WDT Reset WDT Interrupt WDT_CFG ...

Page 86: ...tchdog timeout will cause a chip reset Watchdog reset mode Watchdog counter underflow will reset the MCU and will clear the WDINT flag 1 Watchdog timeout will cause an interrupt Watchdog interrupt mode R W 0 0 WDTEN Watchdog enable 0 Disable 1 Enable When enable the watchdog the WDT_TC value is loaded in the watchdog counter R W 0 7 3 2 Watchdog Timer Constant register WDT_TC Address Offset 0x08 T...

Page 87: ...s Offset 0x0C Bit Name Description Attribute Reset 31 16 WDKEY Watchdog register key Read as 0 When writing to the register you must write 0x5AFA to WDKEY otherwise behavior of writing to the register is ignored W 0 15 0 FV 15 0 Feed value Read as 0x0 0x55AA The watchdog is fed and the WDT_TC value is reloaded in the watchdog counter W 0 ...

Page 88: ...ola SPI bus Synchronous Serial Communication Supports master or slave operation 8 frame FIFO for both transmitter and receiver 4 bit to 16 bit frame Maximum SPI speed of 24 Mbps master or 6 Mbps slave Data transfer format is from MSB or LSB controlled by register The start phase of data sampling location selection is 1 st phase or 2 nd phase controlled register 8 3PIN DESCRIPTION Pin Name Type Des...

Page 89: ...OL clock polarity control bit is HIGH a steady state high value is placed on the CLK pin when data is not being transferred The CPHA clock phase bit controls the phase of the clock on which data is sampled When CPHA 1 the SCK first edge is for data transition and receive and transmit data is at SCK 2 nd edge When CPHA 0 the 1 st bit is fixed already and the SCK first edge is to receive and transmi...

Page 90: ...X TECHNOLOGY CO LTD Page 90 Version 1 5 1 1 0 High Next data LSB bit1 MSB 8 4 2 COMMUNICATION FLOW 8 4 2 1 SINGLE FRAME SCK FS DX DR MSB LSB CS CPOL 0 CPHA 1 CPOL 1 CPHA 0 CPOL 1 CPHA 1 CPOL 0 CPHA 0 DATA MSB MSB LSB DATA LSB MSB LSB 1 2 3 4 5 6 7 8 SPI TI ...

Page 91: ... F0 lsb F1 msb F1 F1 F1 lsb SCK SCK SCK SCK CPOL 0 CPHA 1 CPOL 1 CPHA 0 CPOL 1 CPHA 1 CPOL 0 CPHA 0 SPI TI 8 5AUTO SEL The Auto SEL function is disabled by default and Auto SEL data flow is controlled by HW if enabled If Auto SEL function is disabled SELDIS 1 HW does NOT control SELn pin at all SELn pin is GPIO If Auto SEL function is enabled SELDIS 0 SPI HW controls the SELn activity ...

Page 92: ...TH 2 0 TX FIFO Threshold level 000 TX FIFO threshold level 0 001 TX FIFO threshold level 1 111 TX FIFO threshold level 7 R W 000b 11 8 DL 3 0 Data length DL 3 0 1 0000 0001 Reversed 0010 data length 3 1110 data length 15 1111 data length 16 R W 1111b 7 6 FRESET 1 0 SPI FSM and FIFO Reset bit 00 No effect 01 Reserved 10 Reserved 11 Reset finite state machine and FIFO BUF_BUSY 0 data in shift BUF is...

Page 93: ...High level R W 0 0 MLSB MSB LSB selection bit 0 MSB transmit first 1 LSB transmit first R W 0 8 6 3 SPI n Clock Divider register SPIn _CLKDIV n 0 Address Offset 0x08 Bit Name Description Attribute Reset 31 8 Reserved R 0 7 0 DIV 7 0 SPIn clock divider 0 SCK SSPn_PCLK 2 1 SCK SSPn_PCLK 4 2 SCK SSPn_PCLK 6 X SCK SSPn_PCLK 2X 2 R W 0 8 6 4 SPI n Status register SPIn _STAT n 0 Address Offset 0x0C Bit ...

Page 94: ... the status for each interrupt condition regardless of whether or not the interrupt is enabled in SPIn_IE register This register indicates the status for SPI control raw interrupts An SPI interrupt is sent to the interrupt controller if the corresponding bit in the SPIn_IE register is set Bit Name Description Attribute Reset 31 4 Reserved R 0 3 TXFIFOTHIF TX FIFO threshold interrupt flag 0 No TX F...

Page 95: ...ister when TX_FULL 0 in SPIn_STAT register TX FIFO is not full If the TX FIFO was previously empty and the SPI controller is not busy on the bus transmission of the data will begin immediately Otherwise the data written to this register will be sent as soon as all previous data has been sent and received Read SW can read data from this register when RX_EMPTY 0 in SPIn_STAT registe Rx FIFO is not e...

Page 96: ...ved bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a Repeated START condition Since a Repeated START condition is also the beginning of the next serial transfer the I2C bus will not be released The I2C inte...

Page 97: ...nd diagnostic purposes Generation and detection of 7 bit 10 bit addressing and General Call 9 3PIN DESCRIPTION Pin Name Type Description GPIO Configuration SCLn I O I2C Serial clock Output with Open drain Input depends on GPIOn_CFG SDAn I O I2C Serial data Output with Open drain Input depends on GPIOn_CFG 9 4WAVE CHARACTERISTICS SDA S START Signal P STOP Signal Data Change Allowed Data Change Allo...

Page 98: ...D4 5 D3 6 D2 7 D1 P 9 D6 ACK_ 9 8 D0 D0 Write 1 to ACK bit Start Acknowledge sequence ACK from Master Receiving Data from Slave ACK_ is not sent Write 1 to STO bit Master terminal transfer Data shifted in failing edgeof SCL Write 1 to ACK bit Start Acknowledge sequence 9 5 3 ARBITRATION In the master transmitter mode the arbitration logic checks that every transmitted logic 1 actually appears as a...

Page 99: ...7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R W 0 ACK_ 1 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 P SDA SCL Transmission Data R W 1 D7 9 6 2 SLAVE RECEIVER MODE S Receiving Address ACK_ 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK_ 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 9 8 D0 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 P SDA SCL ACK_ Receiving Data Receiving Data Terminate by Master R W 0 ...

Page 100: ...he I2C bus if it the interface is in master mode and transmits a START condition thereafter If the I2C interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus Note 1 I2CEN shall be set at last 2 HW will assign SCL0 SCL1 and SDA0 SDA1 pins as output pins with open drain function instead of GPIO automatically 3 ACK and NACK bits can t both be 1 when recei...

Page 101: ...serial clock on the SCL line is stretched and the serial transfer is suspended When SCL is HIGH it is unaffected by the state of I2CIF Following events will trigger I2C interrupt if I2C interrupt is enabled in NVIC interrupt controller START Repeat START condition STOP condition Timeout Data byte transmitted or received ACK Transmit or received NACK Transmit or received Bit Name Description Attrib...

Page 102: ...ed R W 0x00 9 7 4 I2C n RX Data register I2Cn_RXDATA n 0 Address Offset 0x0C Bit Name Description Attribute Reset 31 8 Reserved R 0 7 0 DATA 7 0 Contains the data received Read this register when RX_DN 1 R 0x00 9 7 5 I2C n Slave Address 0 register I2Cn_SLVADDR0 n 0 Address Offset 0x10 Only used in slave mode In master mode this register has no effect If this register contains 0x00 the I2C will not...

Page 103: ...x24 Bit Name Description Attribute Reset 31 8 Reserved R 0 7 0 SCLL 7 0 Count for SCL Low Period time SCL Low Period Time SCLL 1 I2C0_PCLK cycle R W 0x04 9 7 9 I2C n Timeout Control register I2Cn_TOCTRL n 0 Address Offset 0x2C Timeout happens when Master Slave SCL remained LOW for TO 32 I2C0_PCLK cycle When I2C timeout occurs the I2C transfer will return to IDLE state and issue a TO interrupt to i...

Page 104: ...l endpoint and 4 configurable endpoints for interrupt bulk transfer Integrated USB transceiver 5V to 3 3V regulator output for D 1 5K ohm internal resistor pull up 10 2 FEATURES Conforms to USB specifications Version 2 0 Supports 1 Full speed USB device address Supports 1 control endpoint with maximum packet size 8 bytes 16 bytes 32 bytes or 64 bytes Supports 4 endpoints configurable for interrupt...

Page 105: ...e starting address in the buffer offset register before the USB function active The USB_EPnBUFOS block is used to control each endpoint s effective starting address The principles to access USB SRAM are as below Each EPnBUFOS setting must be word aligned with 2 LSB bits equal to 0 The maximum length of EPn SRAM buffer is defined by user However each endpoint should have its own EPn SRAM buffer wit...

Page 106: ...oint checking Check the endpoint s request from USB host and set the appropriate bit of registers Firmware is required to handle the rest of the following tasks Coordinate enumeration by decoding USB device requests Fill and empty the FIFOs Reset Suspend Resume coordination Remote wake up function Determine the right interrupt request of USB communication 10 7 USB INTERRUPT The USB function will a...

Page 107: ...P packet followed by a DATA packet to address 0 assigning a new USB address to the device 5 Firmware stores the new address in its USB Device Address Register after the no data control sequence completes 6 The host sends a request for the Device descriptor using the new USB address 7 Firmware decodes the request and retrieves the Device descriptor from program memory tables 8 The host performs a c...

Page 108: ...USB_FRMNO 0x60 R USB Frame Number Register 0x0000_0000 USB_ PHYPRM 0x64 R W USB PHY Parameter Register 0x0000_0000 USB_PHYPRM2 0x6C R W USB PHY Parameter Register 2 0x0000_0000 USB_PS2CTL 0x70 R W USB PS 2 Control Register 0x0000_0000 USB_RWADDR 0x78 R W USB FIFO Read Write Address Register 0x0000_0000 USB_RWDATA 0x7C R W USB FIFO Data Register 0x0000_0000 USB_RWSTATUS 0x80 R W USB FIFO Read Write...

Page 109: ...esume signal is detected 1 Bus resume signal from suspend mode is detected Cleared by write 1 to USB_INSTSC 29 R 0 28 27 Reserved R 0 26 USB_SOF USB SOF packet received flag 0 No USB SOF packet 1 USB SOF packet is received Cleared by write 1 to USB_INSTSC 26 R 0 25 Reserved R 0 24 EP0_PRESETUP EP0 Setup token packet flag This flag will not trigger USB interrupt 0 No EP0 Setup token packet 1 EP0 Se...

Page 110: ... Endpoint 1 ACK transaction flag 0 No Endpoint 1 ACK transacation 1 Endpoint 1 ACK transaction completes Cleared by write 1 to USB_INSTSC 8 R 0 7 4 Reserved R 0 3 EP4_NAK Endpoint 4 NAK transaction flag 0 No EP4 NAK transaction 1 EP4 NAK transaction completes Cleared by write 1 to USB_INSTSC 3 R 0 2 EP3_NAK Endpoint 3 NAK transaction flag 0 No Endpoint 3 NAK transaction 1 EP3 NAK transaction compl...

Page 111: ...ed R 3 EP4_NAKC 0 No effect 1 Clear EP4_NAK bit W 0 2 EP3_NAKC 0 No effect 1 Clear EP3_NAK bit W 0 1 EP2_NAKC 0 No effect 1 Clear EP2_NAK bit W 0 0 EP1_NAKC 0 No effect 1 Clear EP1_NAK bit W 0 10 9 4 USB Device Address Register USB_ADDR Address Offset 0x0C Reset value 0x0000 0000 Bit Name Description Attribute Reset 31 7 Reserved R 0 6 0 UADDR USB device s address R W 0 10 9 5 USB Configuration Re...

Page 112: ... 0 1 EP2_DIR Endpoint 2 IN OUT direction setting 0 EP2 only handshakes to IN token packet 1 EP2 only handshakes to OUT token packet R W 0 0 EP1_DIR Endpoint 1 IN OUT direction setting 0 EP1 only handshakes to IN token packet 1 EP1 only handshakes to OUT token packet R W 0 10 9 6 USB Signal Control Register USB_SGCTL Address offset 0x14 Reset value 0x0000 0000 Bit Name Description Attribute Reset 3...

Page 113: ...T 6 0 Endpoint Byte Count For IN transaction the ENDP_CNT indicates the byte count to be uploaded to host The maximum count for IN transaction should depend on the bMaximumPacketSize0 declaration in USB Device Descriptor and cannot exceed 64 bytes for USB FS device For OUT transaction the ENDP_CNT indicates the byte count received from host R W 0 10 9 8 USB Endpoint n Control Register USB_EPnCTL n...

Page 114: ...ndpoint n Buffer Offset Register USB_EPnBUFOS n 1 4 Address Offset 0x48 0x4C 0x50 0x54 Reset value 0x0000 0000 Bit Name Description Attribute Reset 31 8 Reserved R 0 7 2 OFFSET 5 0 The offset address for each endpoint data buffer The effective offset address is USB_SRAM address EPnBUFOS 7 2 2 b00 Where USB_SRAM address USB_BA 0x100 For endpoint 0 the offset address is fixed as USB_SRAM address R W...

Page 115: ... parameter value R W 0 10 9 14 USB PHY Parameter Register USB_PS2CTL Address Offset 0x70 Reset value 0x0000 0000 Bit Name Description Attribute Reset 31 PS2ENB PS 2 internal 5kohm pull up resistor control bit R W 0 30 4 Reserved R 0 3 SDA PS 2 SDA data buffer R W 0 2 SCK PS 2 SCK data buffer R W 0 1 SDAM PS2 SDA mode control bit R W 0 0 SCKM SCKM PS 2 SCK mode control bit R W 0 10 9 15USB Read Wri...

Page 116: ...from USB FIFO with address RWADDR this bit is automatically cleared as 0 by hardware R W 0 0 W_STATUS Write status of USB FIFO If F W is to write data into USB FIFO set this bit as 1 When hardware has completed the write action RWDATA content has been read as the new data and the new data is written into USB FIFO with address RWADDR this bit is automatically cleared as 0 by hardware R W 0 10 9 18U...

Page 117: ... USB FIFO set this bit as 1 When hardware has completed the read action RWDATA content has been written by the new data read from USB FIFO with address RWADDR this bit is automatically cleared as 0 by hardware R W 0 0 W_STATUS Write status of USB FIFO If F W is to write data into USB FIFO set this bit as 1 When hardware has completed the write action RWDATA content has been read as the new data an...

Page 118: ...ted at a specific base address in the memory map of chip The high performance Flash memory module in chip has the following key features Memory organization the Flash memory is organized as a User ROM User ROM Up to 32K 8 bits divided into 512 pages of 64 Bytes The Flash interface implements instruction access and data access based on the AHB protocol It implements the logic necessary to carry out...

Page 119: ...peration accesses the content of the Flash module through dedicated read senses and provides the requested data The read interface consists of a read controller on one side to access the Flash memory and an AHB interface on the other side to interface with the CPU The main task of the read interface is to generate the control signals to read from the Flash memory as required by the CPU 11 6 PROGRA...

Page 120: ...hange becomes effective only after the MCU has been Reboot User ROM CS0 CS1 CS2 Description WRITER Read O X X Erase O O O WRITER will change the CS level to CS0 Program O O O FW Flash emulation Read O O O Erase O O O Program O O O SWD Read O X X Erase O X X Program O X X Note User may try to change security level from CS2 to CS0 or from CS1 to CS0 HW shall 1 Mass erase the User ROM first User shal...

Page 121: ...n the FLASH_DATA register 5 Wait for the BUSY bit to be reset 6 Set the START bit to start programming 7 Wait for the BUSY bit to be reset 8 Optional Read the programmed value and verify 11 8 3 ERASE The Flash memory can be erased page by page 11 8 3 1 PAGE ERASE A page of the Flash memory can be erased using the Page Erase feature of the FMC To erase a page the procedure below should be followed ...

Page 122: ...3 Reserved R 0 2 ERR Programming error flag 0 Read No error Write Clear this flag 1 Set by HW when Start to Erase Program and find that the address is over page boundary Start to Erase Program and find that the address is illegal ROM size Fill in Data and the address is already over Page Boundary R W 0 1 Reserved R 0 0 BUSY Busy flag 0 Flash operation is not busy 1 Flash operation is in progress T...

Page 123: ...DATA 31 0 Data to be programmed R W 0 11 11 5Flash Address register FLASH_ADDR Address offset 0x10 The Flash address to be erased or programmed should be updated by SW and the PG bit or PER bit shall be set before filling in the Flash address Note Write access to this register is blocked when the BUSY bit in the FLASH_STATUS register is set Bit Name Description Attribute Reset 31 0 FAR 31 0 Flash ...

Page 124: ...d power modes work internal to the ARM Cortex M0 CPU and this ripples through the entire system These differences mean that power measurements should not be made while debugging the results will be higher than during normal operation in an application During a debugging session the SysTick Timer is automatically stopped whenever the CPU is stopped Other peripherals are not affected 12 4 2 DEBUG RE...

Page 125: ...4 3 INTERNAL PULL UP DOWN RESITIORS on SWD PINS To avoid any uncontrolled IO levels the device embeds internal pull up and pull down resistor on the SWD input pins SWDIO JTMS Internal pull up SWCLK JTCK Internal pull down Once a SWD function is disabled by SW the GPIO controller takes control again ...

Page 126: ...arter Kit SN LINK V3 0 USB cable to provide communications between the SN LINK V3 0 and PC IDE Tools KEIL RVMDK SONiX 32 bit MCU Starter Kit SN LINK V3 0 IDE Tools SONiX 32 bit series Embedded ICE Emulator Feature Target s Operating Voltage 2 5V 5 5V Up to 4 hardware break points System clock rate up to 48MHz Oscillator supports IHRC ILRC SONiX 32 bit series Embedded ICE Emulator Limitation SWCLK ...

Page 127: ...2 bit MCU It debugs and programs based on SWD protocol In addition to debugger functions the SN LINK V3 0 also may be used as a programmer to load firmware from PC to MCU for engineering production even mass production SN LINK V3 0 communicates with SONiX 32 bit MCU through SWD interface The pin definition of the Modular cable is as following VDD SWDIO SWCLK VSS ...

Page 128: ...mple platform to develop application as target board not ready The starter kit can be replaced by target board because of integrated SWD debugger circuitry JP3 Micro USB connector JP2 USB Power connector JP1 VDDIO1 power connector Choose the source of VDDIO1 P1 0 P1 5 5 0V 3 3V on board J1 GND connector J2 VDD connector J3 VREG33 output connector U1 SN32F268BF real chip RESET button External reset...

Page 129: ...el input voltage VIH 0 7Vdd Vdd V Low level input voltage VIL Vss 0 3Vdd V Input voltage Vi 0 Vdd V Output voltage Vo 0 Vdd V I O port pull up resistor RPU Vin Vss Vdd 5 0V 30 50 70 KΩ I O port pull down resistor SWD pull down pin RPD Vin 5 0V 30 50 70 KΩ I O High level output source current IOH VOP Vdd 0 5V 6 10 mA I O Low level output sink current IOL VOP Vss 0 5V 12 20 mA FLASH Endurance time T...

Page 130: ...h IC JP3 Pin Assignment Number Name Number Pin Number Pin Number Pin Number Pin Number Pin Number Pin 1 VDD 44 VDD 41 VDD 31 VDD 26 VDD 2 VDD 1 VDD 2 GND 48 VSS 45 VSS 3 VSS 2 VSS 6 VSS 15 VSS 3 CLK 5 P0 1 4 P0 1 5 P0 1 4 P0 1 8 P0 1 6 P0 1 4 CE 5 PGM 26 P3 6 25 P3 6 21 P3 6 18 P3 6 20 P3 6 16 P3 6 6 OE 27 P3 7 26 P3 7 22 P3 7 19 P3 7 21 P3 7 17 P3 7 7 D1 8 D0 9 D3 10 D2 11 D5 12 D4 13 D7 14 D6 15...

Page 131: ... SONiX TECHNOLOGY CO LTD Page 131 Version 1 5 1 1 16 6 6 PACKAGE INFORMATION 16 1 LQFP 48 PIN SYMBOLS MIN NOR MAX mm A 1 6 A1 0 05 0 15 A2 1 35 1 45 c1 0 09 0 16 D 9 00 BSC D1 7 00 BSC E 9 00 BSC E1 7 00 BSC e 0 5 BSC b 0 17 0 27 L 0 45 0 75 L1 1 REF ...

Page 132: ...SN32F260 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 132 Version 1 5 16 2 QFN 46 PIN ...

Page 133: ... SOP 28 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 697 0 705 0 713 17 704 17 907 18 110 E 0 291 0 295 0 299 7 391 7 493 7 595 H 0 394 0 407 0 419 10 008 10 325 10 643 L 0 016 0 033 0 050 0 406 0 838 1 270 θ 0 4 8 0 4 8 ...

Page 134: ... MIN NOR MAX MIN NOR MAX inch mm A 0 08 2 13 A1 0 00 0 01 0 05 0 25 A2 0 06 0 07 0 07 1 63 1 75 1 88 b 0 01 0 01 0 22 0 38 C 0 00 0 01 0 09 0 20 D 0 39 0 40 0 41 9 90 10 20 10 50 E 0 29 0 31 0 32 7 40 7 80 8 20 E1 0 20 0 21 0 22 5 00 5 30 5 60 e 0 0259BSC 0 65BSC L 0 02 0 04 0 04 0 63 0 90 1 03 R 0 00 0 09 θ 0 4 8 0 4 8 ...

Page 135: ...OR MAX inch mm A 0 003 0 030 0 031 0 07 0 75 0 80 A1 0 000 0 001 0 002 0 00 0 02 0 05 A3 0 008 REF 0 20 REF b 0 006 0 008 0 010 0 15 0 20 0 25 D 0 16 BSC 4 00 BSC E 0 16 BSC 4 00 BSC e 0 016 BSC 0 40 BSC L 0 014 0 016 0 018 0 35 0 40 0 45 K 0 008 0 20 PAD SIZE D2 mm E2 mm MIN NOR MAX MIN NOR MAX 115x115 MIL 2 50 2 60 2 65 2 50 2 60 2 65 ...

Page 136: ...SN32F260 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 136 Version 1 5 16 6 QFN 33 PIN ...

Page 137: ...SN32F260 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 137 Version 1 5 16 7 SSOP 24 PIN ...

Page 138: ... MCU production line This note lists the marking definitions of all 32 bit MCU for order or obtaining information 17 2 MARKING INDETIFICATION SYSTEM Title SONiX 32 bit MCU Production ROM Type F Flash memory Material B PB Free Package G Green Package Temperature Range 40 85 Shipping Package W Wafer H Dice K SK DIP P P DIP S SOP X SSOP F LQFP J QFN Device Device Part No SN32 X Part No X X X ...

Page 139: ... Green Package SN32F267JG Flash memory 268 QFN 40 85 Green Package SN32F265JG Flash memory 268 QFN 40 85 Green Package SN32F2641JG Flash memory 268 QFN 40 85 Green Package SN32F264SG Flash memory 268 SOP 40 85 Green Package SN32F264XG Flash memory 268 SSOP 40 85 Green Package SN32F263XG Flash memory 268 SSOP 40 85 Green Package SN32F268W Flash memory 268 Wafer 40 85 SN32F268H Flash memory 268 Dice...

Page 140: ...troller SONiX TECHNOLOGY CO LTD Page 140 Version 1 5 17 4 DATECODE SYSTEM X X X X XXXXX Year Month 1 January 2 February 9 September A October B November C December SONiX Internal Use Day 1 01 2 02 9 09 A 10 B 11 03 2003 04 2004 05 2005 06 2006 ...

Page 141: ...Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unaut...

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