SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 33
Version 1.9
Bit
Name
Description
Attribute
Reset
31:0
CLRPEND[31:0]
Interrupt clear-pending bits.
Write
0: No effect
1: Removes pending state of an interrupt
Read
0: Interrupt is not pending
1: Interrupt is pending
R/W
0
2.3.2.5
IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7)
Address: 0xE000 E400 + 0x4 * n (Refer to Cortex-M0 Spec.)
The interrupt priority registers provide an 8-bit priority field for each interrupt, and each register holds four priority fields.
This means the number of registers is implementation-defined, and corresponds to the number of implemented
interrupts.
Bit
Name
Description
Attribute
Reset
31:24
PRI_(4*n+3)
Each priority field holds a priority value, 0-192. The lower the value, the
greater the priority of the corresponding interrupt. The processor implements
only bits[31:30] of each field, bits [29:24] read as zero and ignore writes. This
means writing 255 to a priority register saves value 192 to the register.
R/W
0
23:16
PRI_(4*n+2)
Each priority field holds a priority value, 0-192. The lower the value, the
greater the priority of the corresponding interrupt. The processor implements
only bits[23:22] of each field, bits [21:16] read as zero and ignore writes. This
means writing 255 to a priority register saves value 192 to the register.
R/W
0
15:8
PRI_(4*n+1)
Each priority field holds a priority value, 0-192. The lower the value, the
greater the priority of the corresponding interrupt. The processor implements
only bits[15:14] of each field, bits [13:8] read as zero and ignore writes. This
means writing 255 to a priority register saves value 192 to the register.
R/W
0
7:0
PRI_4*n
Each priority field holds a priority value, 0-192. The lower the value, the
greater the priority of the corresponding interrupt. The processor implements
only bits[7:6] of each field, bits [5:0] read as zero and ignore writes. This
means writing 255 to a priority register saves value 192 to the register.
R/W
0
2.4 APPLICATION INTERRUPT AND RESET CONTROL (AIRC)
Address: 0xE000 ED0C (Refer to Cortex-M0 Spec)
The entire MCU, including the core, can be reset by SW by setting the SYSRESREQ bit in the AIRC
register in
Cortex-M0 spec.
Note: To write to this register, user must write 0x05FA to the VECTKEY field at the same time, otherwise
the processor ignores the write.
Bit
Name
Description
Attribute
Reset
31:16
VECTKEY
Register key.
Read as unknown. Write 0x05FA to VECTKEY, otherwise the write is
ignored.
R/W
0
15
ENDIANESS
Data endianness implemented
0: Little-endian
1: Big-endian
R
0
14:3
Reserved
R
0
2
SYSRESETREQ
System reset request. This bit read as 0.
0: No effect
1: Requests a system level reset.
W
0
1
VECTCLRACTIVE
Reserved for debug use. This bit read as 0. When writing to the register
you must write 0 to this bit, otherwise behavior is Unpredictable.
W
0
