34
56H5 / 56H1
You can select CAS latency time in HCLKs of 2/2 or 3/3.
The system board designer should have set the values in
this field, depending on the DRAM installed. Do not change
the values in this field unless you change specifications
of the installed DRAM or the installed CPU.
SDRAM Cycle
Length
Choose Enabled or Disabled (default). When Enabled, the
access to the system BIOS ROM addressed at F0000H-
FFFFFH is cached.
System BIOS
Cacheable
This item allows you to select the value in this field, de-
pending on whether the board has paged DRAMs or EDO
(extended data output) DRAMs.
The choice:
EDO 50ns,
EDO 60ns,
Slow,
Medium,
Fast,
Turbo
Bank 0/1 2/3 4/5
DRAM
Choose Enabled or Disabled (default). When enabled, the
access to the VGA RAM addressed is cached.
Video RAM
Cacheable
Choose 4, 8, 16, 32, 64 (default), 128 or 256MB. Memory
map and graphics data structures can reside in a Graph-
ics Aperture. This area is like a linear buffer. BIOS will
automatically report the starting address of this buffer to
the O.S.
AGP Aperture Size
(MB)
DRAM optimization feature: If a memory read is addressed
to a location whose latest write is being held in a buffer
before being written to memory, the read is satisfied
through the buffer contents, and the read is not sent to
the DRAM.
The Choice: Enabled(default), Disabled
DRAM Read
Pipeline
Use default setting.
Cache Pd+CPU Wt
Pipeline
Use default setting.
Cache Timing
Enabled (default): Turn on AC’97 Codec chip controller.
Disabled: Turn off AC’97 Codec chip controller. If user
wants to use external sound card, this function must be
disabled.
OnChip Sound