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High Speed Inter-Chip USB 2.0 Hub and Flash Media Controller

Datasheet

SMSC USB4640/USB4640i

7

Revision 1.0 (06-01-09)

DATASHEET

Chapter 1 Overview

The SMSC USB4640/USB4640i is a Hi-Speed HSIC USB hub and card reader combo solution with
an upstream port compliant to HSIC 1.0, a supplement to the USB 2.0 specification. The two
downstream ports are compliant with the USB 2.0 specification. In addition, The dedicated flash
media reader/writer is internally attached to a 3rd downstream port of the hub as a USB Compound
device.

High Speed Inter-Chip (HSIC) is a digital interconnect bus that enables the use of USB technology
as a low-power chip-to-chip interconnect at speeds up to 480 Mb/s. Please refer to the “High-Speed
Inter-Chip USB Electrical Specification Revision 1.0 as of September 23, 2007” which can be found
at http://www.usb.org/developers/docs/docs. This combo solution supports today’s popular multi-
format flash media cards. This multi-format flash media controller and USB hub combo features two
exposed downstream USB ports available for external peripheral expansion.

The USB4640/USB4640i will attach to an upstream port as a Full-Speed hub or as a Full-/Hi-Speed
hub. The hub supports Low-Speed, Full-Speed, and Hi-Speed (if operating as a Hi-Speed hub)
downstream devices on all of the enabled downstream ports.

All required resistors on the USB ports are integrated into the hub. This includes all series
termination resistors on D+ and D– pins and all required pull-down and pull-up resistors. The over-
current sense inputs for the downstream facing ports have internal pull-up resistors.

The USB4640/USB4640i includes programmable features such as:

PortMap

which provides flexible port mapping and disable sequences. The downstream ports of a

USB4640/USB4640i hub can be reordered or disabled in any sequence to support multiple platform
designs with minimum effort. For any port that is disabled, the USB4640/USB4640i automatically
reorders the remaining ports to match the USB host controller’s port numbering scheme.

PortSwap

which adds per-port programmability to USB differential-

pair pin locations. PortSwap allows direct alignment of USB signals
(D+/D-) to connectors avoiding uneven trace length or crossing of
the USB differential signals on the PCB.

PHYBoost

which enables four programmable levels of USB signal

drive strengths in downstream port transceivers. PHYBoost attempts
to restore USB signal integrity. The diagram on the right shows an
example of Hi-Speed USB eye diagrams before (PHYBoost at 0%)
and after (PHYBoost at 12%) signal integrity restoration in a
compromised system environment.

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Summary of Contents for USB464

Page 1: ...ocations eases PCB design by aligning USB signal traces directly to connectors PHYBoost Programmable USB transceiver drive strength recovers signal integrity 1 For xD Picture CardTM support please obtain a user license from the xD Picture Card License Office 2 Host and media dependent Features Compliance with the following flash media card specifications SD 2 0 MMC 4 2 MS 1 43 MS Pro 1 02 MS Pro H...

Page 2: ...her SMSC literature as well as the Terms of Sale Agreement may be obtained by visiting SMSC s website at http www smsc com SMSC is a registered trademark of Standard Microsystems Corporation SMSC Product names and company names are the trademarks of their respective holders SMSC makes the following part numbered device available for purchase only by customers who are xD Picture Card licensees USB4...

Page 3: ...nfigurations 28 8 3 1 EEPROM SPI Interface 28 8 3 2 EEPROM Data Descriptor 29 8 4 Set bit 7 of bmAttribute to enable the registers in Table 8 4 32 8 4 1 EEPROM Data Descriptor Register Descriptions 32 8 4 2 A0h A7h Device Power Configuration 37 8 4 3 Device ID Strings 39 8 4 4 Hub Controller Configurations 40 8 4 5 Internal Flash Media Controller Extended Configurations 50 8 4 6 I2C EEPROM 52 8 4 ...

Page 4: ...sh Media Controller Datasheet Revision 1 0 06 01 09 4 SMSC USB4640 USB4640i DATASHEET 10 3 DC Electrical Characteristics 57 10 4 Capacitance 61 Chapter 11 GPIO Usage 62 Chapter 12 Package Specifications 63 12 1 Tape and Reel Specifications 64 ...

Page 5: ... States Table 25 Table 7 2 USB4640 USB4640i Reset States Table 25 Table 8 1 Internal Flash Media Controller Configurations 29 Table 8 2 Hub Controller Configurations 31 Table 8 3 Other Internal Configurations 31 Table 8 4 Internal Flash Media Controller Extended Configurations 32 Table 8 5 Port Map Register for Ports 1 2 48 Table 8 6 Port Map Register for Port 3 49 Table 8 7 nRESET Timing for EEPR...

Page 6: ...ly Fuse and Multiple Loads 23 Figure 6 3 Port Power with Ganged Control with Poly Fuse 23 Figure 6 4 SPI ROM Connection 24 Figure 6 5 I2 C Connection 24 Figure 7 1 Pin Reset States 25 Figure 8 1 nRESET Timing for EEPROM Mode 53 Figure 9 1 Typical Crystal Circuit 54 Figure 9 2 Capacitance Formulas 54 Figure 9 3 Ceramic Resonator Usage with SMSC IC 55 Figure 10 1 Supply Rise Time Model 56 Figure 12 ...

Page 7: ...Speed Full Speed and Hi Speed if operating as a Hi Speed hub downstream devices on all of the enabled downstream ports All required resistors on the USB ports are integrated into the hub This includes all series termination resistors on D and D pins and all required pull down and pull up resistors The over current sense inputs for the downstream facing ports have internal pull up resistors The USB...

Page 8: ...2 SD 2 0 SD HS SD HC TransFlash and reduced form factor media 1 4 8 bit MMC 4 2 Memory Stick 1 43 Memory Stick Pro Format 1 02 Memory Stick Pro HG Duo Format 1 01 Memory Stick MS Duo MS HS MS Pro HG MS Pro Memory Stick Duo 1 10 xD Picture Card 1 2 Up to 9 GPIOs Configuration and polarity for special function use The number of actual GPIOs depends on the implementation configuration used One GPIO a...

Page 9: ...to match the OEM s choice of circuit board component selection Port power control and over current detection delay features Configure the delay time for filtering the over current sense inputs Configure the delay time for turning on downstream port power Bus or self powered selection Hub port disable or non removable configurations Flexible port mapping and disable sequencing supports multiple pla...

Page 10: ...ny such technical information SMSC s obligations if any under the Terms of Sale Agreement or any other agreement with any customer or otherwise with respect to infringement including without limitation any obligations to defend or settle claims to reimburse for costs or to pay damages shall not apply to any of the devices made the subject of this document or any software programs related to any of...

Page 11: ... 48 VDD33 47 PLLFILT 46 HSIC_DAT 42 VDD33 1 USBDN_DM2 2 USBDN_DP2 3 USBDN_DM3 4 USBDN_DP3 5 PRTCTL2 6 PRTCTL3 7 SPI_CE_n 8 SPI_CLK GPIO4 SCL 9 VDD33 10 SPI_DI 11 SPI_DO GPIO5 SDA SPI_SPD_SEL 12 21 SD_CLK MS_BS xD_nWP 20 SD_D6 MS_D7 xD_D0 19 SD_D7 MS_D6 xD_D1 18 SD_D0 MS_D4 xD_D2 17 CRFILT 16 SD_D1 MS_D5 xD_D3 15 VDD33 14 GPIO15 SD_nCD 13 GPIO6 SD_WP MS_SCLK xD_D4 23 SD_D5 MS_D1 xD_ALE 22 xD_nWE 24...

Page 12: ...se Switch Driver USB Data Downstream OC Sense Pwr Switch 8051 PROCESSOR SFR RAM XDATA BRIDGE BUS ARBITER ROM 64 K RAM 6 K ADDR MAP GPIOs Program Memory I O Bus PWR_FET0 8 pins GPIO10 CRD_PWR GPIO 3 K total RAM EP2 TX EP2 RX BUS INTFC EP2 RX EP0 TX EP0 RX SIE CTL BRIDGE BUS INTFC FMDU CTL AUTO_CBW PROC FMI BUS INTFC USB Data Downstream Flash Media Cards require Combo socket MS xD SD MMC SDIO OC Sen...

Page 13: ...AL2 RBIAS DOWNSTREAM 2 PORT USB INTERFACE 6 PINS USBDN_DP2 USBDN_DM2 PRTCTL2 PRTCTL3 USBDN_DP3 USBDN_DM3 SECURE DIGITAL MEMORY STICK xD INTERFACE 18 PINS SD_D7 MS_D6 xD_D1 SD_D6 MS_D7 xD_D0 SD_D5 MS_D1 xD_ALE SD_D4 MS_D2 xD_D7 SD_D3 MS_D3 xD_D6 SD_D2 xD_D5 SD_D1 MS_D5 xD_D3 SD_D0 MS_D4 xD_D2 SD_CLK MS_BS xD_nWP SD_CMD MS_D0 xD_CLE GPIO15 SD_nCD GPIO12 MS_INS GPIO6 SD_WP MS_SCLK xD_D4 GPIO14 xD_nCD...

Page 14: ...ash Media Controller Datasheet Revision 1 0 06 01 09 14 SMSC USB4640 USB4640i DATASHEET MISC 5 PINS nRESET TEST GPIO1 LED TXD GPIO2 RXD GPIO10 CRD_PWR POWER 9 PINS 6 VDD33 VDD12 CRFILT PLLFILT TOTAL 48 Table 5 1 USB4640 USB4640i 48 Pin Table ...

Page 15: ...ert or assertion indicates that a signal is active independent of whether that level is represented by a high or low voltage The term negate or negation indicates that a signal is inactive 6 1 USB4640 USB4640i Pin Descriptions Table 6 1 USB4640 USB4640i Pin Descriptions SYMBOL 48 PIN QFN BUFFER TYPE Table 6 2 DESCRIPTION UPSTREAM HSIC INTERFACE HSIC_IMP 39 I HSIC Impedance Control This pin selects...

Page 16: ...s not used XTAL2 44 OCLKx 24 MHz Crystal Output This is the other terminal of the crystal or it is left open when an external clock source is used to drive XTAL1 CLKIN SECURE DIGITAL INTERFACE SD_D 7 0 19 20 23 30 32 33 17 18 I O8PU Secure Digital Data 7 0 These are the bi directional data signals SD_D0 SD_D7 with weak pull up resistors SD_CLK 21 O8 Secure Digital Clock This is an output clock sig...

Page 17: ...tection pin and has a weak internal pull up resistor MS_SCLK 13 O8 Memory Stick System Clock This pin is an output clock signal to the MS device MS_D 7 0 20 19 17 18 32 30 23 24 I O8PD Memory Stick System Data In Out These pins are the bi directional data signals for the MS device In serial mode the most significant bit MSB of each byte is transmitted first by either the memory stick controller MS...

Page 18: ... weak pull down resistor that is permanently enabled GPIO14 xD_nCD 29 I O6 This general purpose pin may be used either as input edge sensitive interrupt input or output Custom firmware is required to activate this function I O8 xD Picture Card Detection GPIO This is a GPIO designated by the default firmware as the xD Picture Card detection pin and has an internal pull up xD_nRE 27 O8PU xD Picture ...

Page 19: ...ired to activate this function This pin is the data pin when the device is connected to the optional I2 C EEPROM I O12 This pin is used to select the speed of the SPI interface During nRESET assertion this pin will be tri stated with the weak pull down resistor enabled When nRESET is negated the value on the pin will be internally latched and the pin will revert to SPI_DO functionality the interna...

Page 20: ...a Device Power Configuration on page 38 for more information nRESET 38 IS RESET input The system uses this active low signal to reset the chip The active low pulse should be at least 1 μs wide TEST 40 I TEST Input Tie this pin to ground for normal operation DIGITAL POWER GROUND CRFILT 15 VDD Core Regulator Filter Capacitor This pin requires a 1 0 μF or greater 20 ESR 0 1Ω capacitor to VSS PLLFILT ...

Page 21: ...tput buffer with an 8 mA sink and an 8 mA source with a weak internal pull up resistor I O8 Input output buffer with an 8 mA sink and an 8 mA source I O8PD Input output buffer with an 8 mA sink and an 8 mA source with a weak internal pull down resistor I O8PU Input output buffer with an 8 mA sink and an 8 mA source with a weak internal pull up resistor O12 Output buffer with a 12 mA sink and a 12 ...

Page 22: ...r will be disabled at that time When port power is enabled the output driver is disabled and the pull up resistor is enabled creating an open drain output If there is an over current situation the USB Power Switch will assert the open drain OCS signal The Schmitt trigger input will detect this event as a low The open drain output does not interfere The internal over current sense filter handles th...

Page 23: ...tput condition means that the pull up resistor is providing 3 3 volts to the anode of the diode If there is an over current situation the poly fuse will open This will cause the cathode of the diode to go to zero volts The anode of the diode will be at 0 7 volts and the Schmitt trigger input will register this as a low resulting in an over current detection The open drain output does not interfere...

Page 24: ...ons The SPI ROM required for the USB4640 USB4640i is a recommended minimum of 1 Mbit and support either 30 MHz or 60 MHz The frequency used is set using the SPI_SPD_SEL For 30 MHz operation this pin must be pulled to ground through a 100 kΩ resistor For 60 MHz operation this pin must pulled up through a 100 kΩ resistor The SPI_SPD_SEL pin is used to choose the speed of the SPI interface During nRE...

Page 25: ... PU Hardware enables pull up PD Hardware enables pull down none Hardware disables pad Hardware disables function Z Hardware disables pad Both output driver and input buffers are disabled Table 7 2 USB4640 USB4640i Reset States Table RESET STATE PIN PIN NAME FUNCTION INPUT OUTPUT PU PD 1 USBDN_DM2 USBDN_DM2 IP PD 2 USBDN_DP2 USBDN_DP2 IP PD 3 USBDN_DM3 USBDN_DM3 IP PD 4 USBDN_DP3 USBDN_DP3 IP PD 6 ...

Page 26: ...D1 none Z 20 SD_D6 MS_D7 xD_D0 none Z 21 SD_CLK MS_BS xD_nWP none Z 22 xD_nWE xD_nWE Z 23 SD_D5 MS_D1 xD_ALE none Z 24 SD_CMD MS_D0 xD_CLE none Z 26 xD_nCE xD_nCE Z 27 xD_nRE xD_nRE Z 28 xD_nB R xD_nB R Z 29 GPIO14 xD_nCD GPIO IP PU 30 SD_D4 MS_D2 xD_D7 none Z 31 GPIO12 MS_INS GPIO IP PU 32 SD_D3 MS_D3 xD_D6 none Z 33 SD_D2 xD_D5 none Z 35 GPIO10 CRD_PWR GPIO Z 36 GPIO2 RXD GPIO 0 37 GPIO1 LED TXD...

Page 27: ...Media Controller Datasheet SMSC USB4640 USB4640i 27 Revision 1 0 06 01 09 DATASHEET 42 HSIC_DAT HSIC_DAT IP 43 HSIC_STROBE HSIC_STROBE IP Table 7 2 USB4640 USB4640i Reset States Table continued RESET STATE PIN PIN NAME FUNCTION INPUT OUTPUT PU PD ...

Page 28: ... two principal ways to configure the hub via the internal default settings or by settings stored in an external EEPROM or SPI Flash device 8 1 1 1 Power Switching Polarity The hub will only support active high power controllers 8 2 Card Reader The SMSC USB4640 USB4640i is fully compliant with the following flash media card reader specifications Secure Digital 2 0 MultiMediaCard 4 2 SD 2 0 HS SD HC...

Page 29: ...ns ADDRESS REGISTER NAME DESCRIPTION INTERNAL DEFAULT VALUE 00h USB_SER_LEN USB Serial String Descriptor Length 1Ah 01h USB_SER_TYP USB Serial String Descriptor Type 03h 02h 19h USB_SER_NUM USB Serial Number 000008264001 See Note 8 1 1Ah 1Bh USB_VID USB Vendor Identifier 0424 1Ch 1Dh USB_PID USB Product Identifier 4040 1Eh USB_LANG_LEN USB Language String Descriptor Length 04h 1Fh USB_LANG_TYP USB...

Page 30: ...Note 8 2 A6h SD_PWR_LB Secure Digital Device Power Lo byte 00h A7h SD_PWR_HB Secure Digital Device Power Hi byte 0Ah A8h LED_BLK_INT LED Blink Interval 02h A9h LED_BLK_DUR LED Blink After Access 28h AAh B0h DEV0_ID_STR Device 0 Identifier String N A B1h B7h DEV1_ID_STR Device 1 Identifier String MS B8h BEh DEV2_ID_STR Device 2 Identifier String SM See Note 8 2 BFh C5h DEV3_ID_STR Device 3 Identifi...

Page 31: ...n Data Byte 2 28h E6h CFG_DAT_BYT3 Configuration Data Byte 3 00h E7h NR_DEVICE Non Removable Devices 02h E8h PORT_DIS_SP Port Disable Self 00h E9h PORT_DIS_BP Port Disable Bus 00h EAh MAX_PWR_SP Max Power Self 01h EBh MAX_PWR_BP Max Power Bus 32h ECh HC_MAX_C_SP Hub Controller Max Current Self 01h EDh HC_MAX_C_BP Hub Controller Max Current Bus 32h EEh PWR_ON_TIME Power on Time 32h EFh BOOST_UP Boo...

Page 32: ...rations ADDRESS REGISTER NAME DESCRIPTION INTERNAL DEFAULT VALUE 100h 106h CLUN0_ID_STR Combo LUN 0 Identifier String COMBO 107h 10Dh CLUN1_ID_STR Combo LUN 1 Identifier String COMBO 10Eh 114h CLUN2_ID_STR Combo LUN 2 Identifier String COMBO 115h 11Bh CLUN3_ID_STR Combo LUN 3 Identifier String COMBO 11Ch 122h CLUN4_ID_STR Combo LUN 4 Identifier String COMBO 123h 129h Not Applicable N A 12Ah 145h N...

Page 33: ...um BYTE NAME DESCRIPTION 1 0 USB_PID This ID is unique for every product The product ID is assigned by the vendor BYTE NAME DESCRIPTION 0 USB_LANG_LEN USB language ID string descriptor length as defined by Section 9 6 7 String of the USB 2 0 Specification Revision 2 0 2000 This field is the bLength which describes the size of the string descriptor in bytes BYTE NAME DESCRIPTION 1 USB_LANG_TYP USB ...

Page 34: ...as defined by Section 9 6 7 String of the USB 2 0 Specification Revision 2 0 2000 This field is the bDescriptorType which is a constant value associated with a string descriptor type BYTE NAME DESCRIPTION 15 2 USB_MFR_STR The maximum string length is 28 characters BYTE NAME DESCRIPTION 59 16 Reserved Reserved BYTE NAME DESCRIPTION 0 USB_PRD_STR _LEN USB product string descriptor length as defined ...

Page 35: ... configuration the bus powered SMSC hub along with all associated hub circuitry any embedded devices if part of a compound device and 100 mA per externally available downstream port must consume no more than 500 mA of current The current consumption is system dependent and the OEM must ensure that the USB 2 0 Specification is not violated When configured as a self powered device 1 mA of current is...

Page 36: ...high 7 Extended Configuration Enable 1 This bit must be set to 1 to enable editing updating and reading from registers 100h 17Fh 0 The internal configuration is loaded When this bit is not set and it equals 0 It will not read from registers 100h 17Fh 1 ATT_HLB 3 0 Always reads 0 4 Activity LED True Polarity 1 Activity LED to Low True 0 default Activity LED polarity to High True 5 Common Media Inse...

Page 37: ...e ignored unless the Enable Device Power Configuration bit is set See Section 8 4 1 19 9Ch 9Fh Attribute Byte Descriptions on page 36 8 4 2 1 A0h A1h Memory Stick Device Power Configuration 8 4 2 2 A2h A3h Not Applicable 2 ATT_LHB 0 Attach on Card Insert Detach on Card Removal 1 Attach on Insert is enabled 0 default Attach on Insert is disabled 1 Always reads 0 2 Enable Device Power Configuration ...

Page 38: ...bled FET TYPE BITS BIT TYPE DESCRIPTION 0 FET Lo Byte SD_PWR_LB 3 0 Low Nibble 0000b Disabled 1 7 4 High Nibble 2 FET Hi Byte SD_PWR_HB 3 0 Low Nibble 0000b Disabled 0001b External FET enabled 1000b Internal FET with 100 mA power limit 1010b Internal FET with 200 mA power limit 3 7 4 High Nibble 0000b Disabled BYTE NAME DESCRIPTION 0 LED_BLK_INT The blink rate is programmable in 50 ms intervals Th...

Page 39: ...Identifier String 8 4 3 4 BFh C5h Device 3 Identifier String 8 4 3 5 C6h CDh Inquiry Vendor String 8 4 3 6 CEh D2h Inquiry Product String BYTE NAME DESCRIPTION 6 0 DEV0_ID_STR Not applicable BYTE NAME DESCRIPTION 6 0 DEV1_ID_STR This ID string is associated with the Memory Stick device BYTE NAME DESCRIPTION 6 0 DEV2_ID_STR This ID string is associated with the Smart Media Note 8 2 device BYTE NAME...

Page 40: ...a device controller SD MMC SM Note 8 2 and MS to a Logical Unit Number LUN The device reports the mapped LUNs to the USB host in the USB descriptor during enumeration The icon installer associates custom icons with the LUNs specified in these fields Setting a register to FF indicates that the device is not mapped Setting all of the DEV_LUN_MAP registers for all devices to FF forces the use of the ...

Page 41: ...ELF_BUS_PWR Self or Bus Power Selects between self and bus powered operation The hub is either self powered draws less than 2 mA or bus powered limited to 100 mA maximum power prior to being configured by the host controller When configured as a bus powered device the SMSC hub consumes less than 100 mA of current prior to being configured After configuration the bus powered SMSC hub along with all...

Page 42: ...simultaneously ganged or port power is individually switched on and off on a port by port basis individual The ability to support power enabling on a port or ganged basis is dependent upon the hardware implementation 0 Ganged switching all ports together 1 Individual port by port switching BIT NAME DESCRIPTION 7 6 Reserved Reserved 5 4 OC_TIMER OverCurrent Timer Over current timer delay 00 50 ns 0...

Page 43: ...ation Reset 0x00 1 Port Map mode The mode enables remapping via the registers defined below Register 30FBh Port Map 12 Reset 0x00 Register 30FCh Port Map 3 Reset 0x00 2 0 Reserved Reserved BIT BYTE NAME DESCRIPTION 7 0 NR_DEVICE Indicates which port s include non removable devices 0 Port is removable 1 Port is non removable Informs the host if one of the active ports has a permanent device that is...

Page 44: ...re ports 0 Port is available 1 Port is disabled During self powered operation this register selects the ports which will be permanently disabled The ports are unavailable to be enabled or enumerated by a host controller The ports can be disabled in any order the internal logic will automatically report the correct number of enabled ports to the USB host and will reorder the active ports in order t...

Page 45: ...with the combined power consumption of all associated circuitry on the board This value does NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device Note The USB 2 0 Specification does not permit this value to exceed 100 mA A value of 50 decimal indicates 100 mA which is the default value BIT BYTE NAME DESCRIPTION 7 0 HC_MAX_C_BP Value i...

Page 46: ...IT NAME DESCRIPTION 7 6 Reserved Reserved 5 4 BOOST_IOUT_3 Upstream USB electrical signaling drive strength boost bit for downstream port 3 00 Normal electrical drive strength No boost 01 Elevated electrical drive strength Low approximately 4 boost 10 Elevated electrical drive strength Medium approximately 8 boost 11 Elevated electrical drive strength High approximately 12 boost 3 2 BOOST_IOUT_2 U...

Page 47: ...d DM pins for ease of board routing to devices and connectors 0 USB D functionality is associated with the DP pin and D functionality is associated with the DM pin 1 USB D functionality is associated with the DM pin and D functionality is associated with the DP pin Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Controls physical port 3 Bit 2 Controls physical port 2 Bit 1 Reserv...

Page 48: ...ed see PRTMAP_EN in Register 08h Configuration Data Byte 3 the hub s downstream port numbers can be remapped to different logical port numbers assigned by the host Note The OEM must ensure that contiguous logical port numbers are used starting from number 1 up to the maximum number of enabled ports this ensures that the hub s ports are numbered in accordance with the way a host will communicate wi...

Page 49: ...physical port number When remapping mode is enabled see PRTMAP_EN in Register 08h Configuration Data Byte 3 the hub s downstream port numbers can be remapped to different logical port numbers assigned by the host Note The OEM must ensure that contiguous logical port numbers are used starting from number 1 up to the maximum number of enabled ports this ensures that the hub s ports are numbered in a...

Page 50: ...configuration area The signature must be set to ATA2 for USB4640 USB4640i BYTE NAME DESCRIPTION 6 0 CLUN0_ID_STR If the device to LUN mapping bytes have configured this LUN to be a combo LUN then these strings will be used to identify the LUN rather than the device identifier strings BYTE NAME DESCRIPTION 6 0 CLUN1_ID_STR If the device to LUN bytes have configured this LUN to be a combo LUN then t...

Page 51: ...icon displayed for one or more interfaces If this field is set to FF the program assumes that you are using the default value and icons will be configured per the default configuration BYTE NAME DESCRIPTION 4 0 DEV_LUN_MAP These registers map a device controller SD MMC SM Note 8 2 and MS to a Logical Unit Number LUN The device reports the mapped LUNs to the USB host in the USB descriptor during en...

Page 52: ...Programming The EEPROM can be programmed via automatic test equipment ATE Pulling nRESET low tri states the device s EEPROM interface and allows an external source to program the EEPROM 8 5 Default Configuration Option The SMSC device can be configured via its internal default configuration Please see Section 8 3 2 EEPROM Data Descriptor for specific details on how to enable default configuration ...

Page 53: ...s 4 Clears all TT buffers 5 Moves device from suspended to active if suspended 6 Complies with Section 11 10 of the USB 2 0 Specification for behavior after completion of the reset sequence The host then configures the device and the device s downstream port devices in accordance with the USB 2 0 Specification Table 8 7 nRESET Timing for EEPROM Mode NAME DESCRIPTION MIN TYP MAX UNITS t1 nRESET ass...

Page 54: ...nce Formulas However the OEM PCB itself may present a parasitic capacitance between XTAL1 and XTAL2 For an accurate calculation of C1 and C2 take the parasitic capacitance between traces XTAL1 and XTAL2 into account Note 9 2 Each of these capacitance values is typically approximately 18 pF SYMBOL DESCRIPTION IN ACCORDANCE WITH C0 Crystal shunt capacitance Crystal manufacturer s specification See N...

Page 55: ...350 ppm Jitter 100 ps rms The external clock is recommended to conform to the signaling level designated in the JESD76 2 specification on 1 8 V CMOS Logic XTAL2 should be treated as a no connect 9 3 1 I2 C EEPROM Frequency is fixed at 58 6 kHz 20 9 3 2 USB 2 0 The SMSC device conforms to all voltage power and timing characteristics and specifications as set forth in the USB 2 0 Specification Pleas...

Page 56: ...r is switched on or off In addition voltage transients on the AC power line may appear on the DC output When this possibility exists a clamp circuit should be used Figure 10 1 Supply Rise Time Model PARAMETER SYMBOL MIN MAX UNITS COMMENTS Storage Temperature TSTOR 55 150 C Lead Temperature C Please refer to JEDEC specification J STD 020D 3 3 V supply voltage VDD33 0 5 4 0 V Voltage on USB and USB ...

Page 57: ... output tolerance of 1 must be used if the output of the internal power FET s must support a 5 tolerance 3 3 V supply rise time tRT 0 400 μs Figure 10 1 Voltage on USB and USB pins 0 3 5 5 V If any 3 3 V supply voltage drops below 3 0 V then the MAX becomes 3 3 V supply voltage 0 5 5 5 Voltage on any signal pin 0 3 VDD33 V Voltage on XTAL1 0 3 2 0 V Voltage on XTAL2 0 3 2 0 V PARAMETER SYMBOL MIN ...

Page 58: ... 10 10 μA μA VIN 0 VIN VDD33 I O6 I OD6PU Type Buffers Low Output Level High Output Level Output Leakage Pull Down Pull Up VOL VOH IOL PD PU VDD33 0 4 10 72 58 0 4 10 V V µA μA μA IOL 6 mA VDD33 3 3 V IOH 6 mA VDD33 3 3 V VIN 0 to VDD33 Note 10 1 O8 O8PD 08PU I O8 I O8PD and I O8PU Type Buffers Low Output Level High Output Level Output Leakage Pull Down Pull Up VOL VOH IOL PD PU VDD33 0 4 10 72 58...

Page 59: ...0 4 On Resistance Note 10 4 Output Voltage Rise Time IOUT IOUT RDSON tDSON 200 100 2 1 800 mA mA Ω μs VdropFET 0 46 V VdropFET 0 23 V IFET 70 mA CLOAD 10 μF Integrated Power FET Set to 100 mA Output Current Note 10 4 Short Circuit Current Limit On Resistance Note 10 4 Output Voltage Rise Time IOUT ISC RDSON tDSON 100 140 2 1 800 mA mA Ω μs VdropFET 0 22 V VoutFET 0 V IFET 70 mA CLOAD 10 μF Integra...

Page 60: ...the commercial temperature range of 0 C to 70 C The USB4640i supports the industrial temperature range of 40 C to 85 C Supply Current Unconfigured Hi Speed Host USB4640 USB4640i Full Speed Host USB4640 USB4640i ICCINTHS ICCINTHS ICCINITFS ICCINITFS TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA Note 10 6 Supply Current Configured Hi Speed Host 1 downstream port USB4640 USB4640i IHCH1 IHCH1 TBD TBD TB...

Page 61: ...0 06 01 09 DATASHEET 10 4 Capacitance TA 25 C fc 1 MHz VDD33 3 3 V Table 10 1 Pin Capacitance PARAMETER SYMBOL LIMITS UNIT TEST CONDITION MIN TYP MAX Clock Input Capacitance CXTAL 2 pF All pins except USB pins and pins under test are tied to AC ground Input Capacitance CIN 10 pF Output Capacitance COUT 20 pF ...

Page 62: ...L SYMBOL DESCRIPTION AND NOTE GPIO1 H LED TxD LED indicator Serial port transmit line GPIO2 H RxD Serial port receive line GPIO4 H SCL Serial EEPROM clock GPIO5 H SDA Serial EEPROM data GPIO6 L SD_WP Secure Digital card write protect assertion GPIO10 L CRD_PWR_CTRL Card power control GPIO12 L MS_nCD Memory Stick card detect GPIO14 L xD_nCD xD Picture card detect GPIO15 L SD_nCD Secure Digital card...

Page 63: ...High Speed Inter Chip USB 2 0 Hub and Flash Media Controller Datasheet SMSC USB4640 USB4640i 63 Revision 1 0 06 01 09 DATASHEET Chapter 12 Package Specifications Figure 12 1 USB4640 USB4640i 48 Pin QFN ...

Page 64: ...h Speed Inter Chip USB 2 0 Hub and Flash Media Controller Datasheet Revision 1 0 06 01 09 64 SMSC USB4640 USB4640i DATASHEET 12 1 Tape and Reel Specifications Figure 12 2 48 Pin Package Tape Specifications ...

Page 65: ...High Speed Inter Chip USB 2 0 Hub and Flash Media Controller Datasheet SMSC USB4640 USB4640i 65 Revision 1 0 06 01 09 DATASHEET Figure 12 3 48 Pin Package Reel Specifications ...

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