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SMSC LAN9514

Revision 1.0 (04-20-09)

DATASHEET

Datasheet

PRODUCT FEATURES

LAN9514

USB Hub with Integrated

10/100 Ethernet Controller

Highlights

Four downstream ports, one upstream port

— Four integrated downstream USB 2.0 PHYs
— One integrated upstream USB 2.0 PHY

Integrated 10/100 Ethernet MAC with full-duplex

support

Integrated 10/100 Ethernet PHY

with HP Auto-MDIX

Implements Reduced Power Operating Modes

Minimized BOM Cost

— Single 25 MHz crystal (Eliminates cost of separate

crystals for USB and Ethernet)

— Built-in Power-On-Reset (POR) circuit (Eliminates

requirement for external passive or active reset)

Target Applications

Desktop PCs

Notebook PCs

Printers

Game Consoles

Embedded Systems

Docking Stations

Key Benefits

USB Hub

— Fully compliant with Universal Serial Bus Specification

Revision 2.0

— HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps)

compatible

— Four downstream ports, one upstream port
— Port mapping and disable support
— Port Swap: Programmable USB diff-pair pin location
— PHY Boost: Programmable USB signal drive strength
— Select presence of a permanently hardwired USB

peripheral device on a port by port basis

— Advanced power saving features
— Downstream PHY goes into low power mode when port

power to the port is disabled

— Full Power Management with individual or ganged

power control of each downstream port.

— Integrated USB termination Pull-up/Pull-down resistors
— Internal short circuit protection of USB differential signal

pins

High-Performance 10/100 Ethernet Controller

— Fully compliant with IEEE802.3/802.3u
— Integrated Ethernet MAC and PHY
— 10BASE-T and 100BASE-TX support
— Full- and half-duplex support with flow control
— Preamble generation and removal
— Automatic 32-bit CRC generation and checking
— Automatic payload padding and pad removal
— Loop-back modes
— TCP/UDP checksum offload support
— Flexible address filtering modes

– One 48-bit perfect address
– 64 hash-filtered multicast addresses
– Pass all multicast
– Promiscuous mode
– Inverse filtering
– Pass all incoming with status report

— Wakeup packet support
— Integrated Ethernet PHY

– Auto-negotiation
– Automatic polarity detection and correction
– HP Auto-MDIX
– Energy Detect

Power and I/Os

— Three PHY LEDs
— Eight GPIOs
— Supports bus-powered and self-powered operation
— Internal 1.8v core supply regulator
— External 3.3v I/O supply

Miscellaneous features

— Optional EEPROM
— Optional 24MHz reference clock output for partner hub
— IEEE 1149.1 (JTAG) Boundary Scan

Software

— Windows 2000/XP/Vista Driver
— Linux Driver
— Win CE Driver
— MAC OS Driver
— EEPROM Utility

Packaging

— 64-pin QFN, lead-free RoHS compliant

Environmental

— Commercial Temperature Range (0°C to +70°C)
— ±8kV HBM without External Protection Devices
— ±8kV contact mode (IEC61000-4-2)
— ±15kV air-gap discharge mode (IEC61000-4-2)

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Summary of Contents for LAN9514

Page 1: ...ividual or ganged power control of each downstream port Integrated USB termination Pull up Pull down resistors Internal short circuit protection of USB differential signal pins High Performance 10 100 Ethernet Controller Fully compliant with IEEE802 3 802 3u Integrated Ethernet MAC and PHY 10BASE T and 100BASE TX support Full and half duplex support with flow control Preamble generation and remova...

Page 2: ...own as anomalies which may cause the product s functions to deviate from published specifications Anomaly sheets are available upon request SMSC products are not designed intended authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage Any and all such uses without prior written approval o...

Page 3: ... 2 1 2 Port Power Control Using a Poly Fuse 17 2 2 Buffer Types 19 Chapter 3 EEPROM Controller EPC 20 3 1 EEPROM Format 20 3 1 1 Hub Configuration 23 3 2 EEPROM Defaults 33 3 3 EEPROM Auto Load 33 3 4 An Example of EEPROM Format Interpretation 34 Chapter 4 Operational Characteristics 39 4 1 Absolute Maximum Ratings 39 4 2 Operating Conditions 39 4 3 Power Consumption 40 4 3 1 Operational Current C...

Page 4: ...LAN9514 64 QFN Pin Assignments TOP VIEW 9 Figure 2 2 Port Power Control with USB Power Switch 16 Figure 2 3 Port Power Control with Poly Fuse 17 Figure 2 4 Port Power with Ganged Control with Poly Fuse 18 Figure 4 1 Output Equivalent Test Load 43 Figure 4 1 EEPROM Timing 44 Figure 5 1 LAN9514 64 QFN Package Definition 46 Figure 5 2 LAN9514 Recommended PCB Land Pattern 47 ...

Page 5: ...able 3 5 Config Data Byte 2 Register CFG2 Format 30 Table 3 6 Config Data Byte 3 Register CFG3 Format 31 Table 3 7 Boost_Up Register BOOSTUP Format 31 Table 3 8 Boost_5 Register BOOST5 Format 31 Table 3 9 Boost_4 2 Register BOOST42 Format 32 Table 3 10 Status Command Register STCD Format 32 Table 3 11 EEPROM Defaults 33 Table 3 12 Dump of EEPROM Memory 34 Table 3 13 EEPROM Example 256 Byte EEPROM ...

Page 6: ...ping and disabling sequences The downstream ports of the LAN9514 hub can be reordered or disabled in any sequence to support multiple platform designs with minimum effort For any port that is disabled the LAN9514 automatically reorders the remaining ports to match the USB host controller s port numbering scheme PortSwap which adds per port programmability to USB differential pair pin locations Por...

Page 7: ...to initiate a USB remote wakeup The 10 100 Ethernet PHY integrates an IEEE 802 3 physical layer for twisted pair Ethernet applications The PHY block includes support for auto negotiation full or half duplex configuration auto polarity correction and Auto MDIX Minimal external components are required for the utilization of the integrated PHY The Ethernet controller implements four USB endpoints Con...

Page 8: ... 0 04 20 09 8 SMSC LAN9514 DATASHEET SUSPEND1 Supports GPIO and Link Status Change for remote wakeup events This suspend state consumes less power than SUSPEND0 SUSPEND2 Supports only GPIO assertion for a remote wakeup event This is the default suspend mode for the LAN9514 ...

Page 9: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 47 46 45 44 43 42 41 40 39 38 37 36 35 34 63 62 61 60 59 58 57 56 55 54 53 52 51 50 TEST1 nRESET VBUS_DET VDD33A USBDP5 USBDM5 USBDP4 USBDM4 VDD33A USBDP3 USBDM3 USBDP2 USBDM2 VDD33IO CLK24_OUT CLK24_EN GPIO7 GPIO6 AUTOMDIX_EN TEST3 VDD33IO VDD18CORE GPIO5 GPIO4 GPIO3 TEST2 VDD33A RXP RXN VDD33A TXP TXN VDD33A USBDM0 USBDP0 XO XI VDD18USBPLL USBRBIAS TDI T...

Page 10: ... tied high if it is not used 1 JTAG Test Mode Select TMS IS This pin functions as the JTAG test mode select 1 JTAG Test Data Input TDI IS This pin functions as the JTAG data input 1 JTAG Test Data Out TDO O12 This pin functions as the JTAG data output 1 JTAG Test Clock TCK IS This pin functions as the JTAG test clock The maximum operating frequency of this clock is 25MHz Table 2 3 Miscellaneous Pi...

Page 11: ...pin is fully programmable as either a push pull output an open drain output or a Schmitt triggered input 1 General Purpose I O 4 GPIO4 IS O8 OD8 PU This General Purpose I O pin is fully programmable as either a push pull output an open drain output or a Schmitt triggered input 1 General Purpose I O 5 GPIO5 IS O8 OD8 PU This General Purpose I O pin is fully programmable as either a push pull output...

Page 12: ...BOL BUFFER TYPE DESCRIPTION 1 Upstream USB DMINUS 0 USBDM0 AIO Upstream USB DMINUS signal 1 Upstream USB DPLUS 0 USBDP0 AIO Upstream USB DPLUS signal 1 Downstream USB DMINUS 2 USBDM2 AIO Downstream USB peripheral 2 DMINUS signal 1 Downstream USB DPLUS 2 USBDP2 AIO Downstream USB peripheral 2 DPLUS signal 1 Downstream USB DMINUS 3 USBDM3 AIO Downstream USB peripheral 3 DMINUS signal 1 Downstream US...

Page 13: ...t this pin is used to sample the output signal from an external current monitor for downstream USB peripheral 4 An overcurrent condition is indicated when the signal is low Refer to Section 2 1 for additional information 1 USB Port Power Control 5 PRTCTL5 IS OD12 PU When used as an output this pin enables power to downstream USB peripheral 5 When used as an input this pin is used to sample the out...

Page 14: ...Positive RXP AIO Positive input of the Ethernet receiver The receive data inputs may be swapped internally with transmit data outputs when Auto MDIX is enabled 7 3 3V Analog Power Supply VDD33A P Refer to the LAN9514 reference schematics for connection information 1 External PHY Bias Resistor EXRES AI Used for the internal bias circuits Connect to an external 12 4K 1 0 resistor to ground 1 Etherne...

Page 15: ...FDX_LED GPIO0 36 GPIO4 52 RXP 5 VDD33A 21 nLNKA_LED GPIO1 37 GPIO5 53 RXN 6 USBDM4 22 nSPD_LED GPIO2 38 VDD18CORE 54 VDD33A 7 USBDP4 23 EECLK 39 VDD33IO 55 TXP 8 USBDM5 24 EECS 40 TEST3 56 TXN 9 USBDP5 25 EEDO 41 AUTOMDIX_EN 57 VDD33A 10 VDD33A 26 EEDI 42 GPIO6 58 USBDM0 11 VBUS_DET 27 VDD33IO 43 GPIO7 59 USBDP0 12 nRESET 28 nTRST 44 CLK24_EN 60 XO 13 TEST1 29 TMS 45 CLK24_OUT 61 XI 14 PRTCTL2 30 ...

Page 16: ...ed at that time When port power is enabled the output driver is disabled and the pull up resistor is enabled creating an open drain output If there is an over current situation the USB Power Switch will assert the open drain OCS signal The schmitt trigger input will recognize this situation as a low The open drain output does not interfere The overcurrent sense filter handles the transient conditi...

Page 17: ...d and the pull up resistor is enabled which creates an open drain output This means that the pull up resistor is providing 3 3 volts to the anode of the diode If there is an over current situation the poly fuse will open This will cause the cathode of the diode to go to 0 volts The anode of the diode will be at 0 7 volts and the Schmidt trigger input will register this as a low resulting in an ove...

Page 18: ...MSC LAN9514 DATASHEET Many customers use a single poly fuse to power all their devices For the ganged situation all power control pins must be tied together Figure 2 4 Port Power with Ganged Control with Poly Fuse USB Device Poly Fuse 5V USB Device PRTCTL2 LAN9514 PRTCTL3 PRTCTL4 PRTCTL5 ...

Page 19: ...nabled Note Internal pull up resistors prevent unconnected inputs from floating Do not rely on internal resistors to drive signals external to LAN9514 When connected to a load that must be pulled high an external resistor must be added PD 50uA typical internal pull down Unless otherwise noted in the pin description internal pull downs are always enabled Note Internal pull down resistors prevent un...

Page 20: ...Table 3 1 illustrates the format in which data is stored inside of the EEPROM Note the EEPROM offsets are given in units of 16 bit word offsets A length field with a value of zero indicates that the field does not exist in the EEPROM The device will use the field s HW default value in this case Note For Device Descriptors the only valid values for the length are 0 and 18 Note For Configuration and...

Page 21: ... Hi Speed Device Descriptor Length bytes 17h Hi Speed Device Descriptor Word Offset 18h Hi Speed Configuration and Interface Descriptor Length bytes 19h Hi Speed Configuration and Interface Descriptor Word Offset 1Ah Full Speed Device Descriptor Length bytes 1Bh Full Speed Device Descriptor Word Offset 1Ch Full Speed Configuration and Interface Descriptor Length bytes 1Dh Full Speed Configuration ...

Page 22: ... Time Register PWRT 31h Boost_Up Register BOOSTUP 32h Boost_5 Register BOOST5 33h Boost_4 2 Register BOOST42 34h RESERVED 35h Port Swap Register PRTSP 36h Port Remap 12 Register PRTR12 37h Port Remap 34 Register PRTR34 38h Port Remap 5 Register PRTR5 39h Status Command Register STCD Table 3 2 Configuration Flags Description BIT NAME DESCRIPTION 7 3 RESERVED 00000b 2 Remote Wakeup Support 0 The dev...

Page 23: ...signed by the OEM 95h 24h Device ID LSB Register DIDL Least Significant Byte of the Device ID This is a 16 bit device release number in BCD format assigned by the OEM 00h 25h Device ID MSB Register DIDM Most Significant Byte of the Device ID This is a 16 bit device release number in BCD format assigned by the OEM Note 3 1 26h Config Data Byte 1 Register CFG1 Refer to Table 3 4 Config Data Byte 1 R...

Page 24: ...e USB host and will reorder the active ports in order to ensure proper function Bit 7 RESERVED Bit 6 RESERVED Bit 5 1 Port 5 disabled Bit 4 1 Port 4 disabled Bit 3 1 Port 3 disabled Bit 2 1 Port 2 disabled Bit 1 1 Port 1 disabled Bit 0 is RESERVED always 0b 00h 2Ch Max Power Self Register MAXPS Value in 2mA increments that the Hub consumes from an upstream port VBUS when operating as a self powere...

Page 25: ...r on Time Register PWRT The length of time that it takes in 2mS intervals from the time the host initiated power on sequence begins on a port until power is good on that port System software uses this value to determine how long to wait before accessing a powered on port 32h 31h Boost_Up Register BOOSTUP Refer to Table 3 7 Boost_Up Register BOOSTUP Format on page 31 for details 00h 32h Boost_5 Reg...

Page 26: ...ical port numbers assigned by the host Note The OEM must ensure that Contiguous Logical Port Numbers are used starting from 1 up to the maximum number of enabled ports This ensures that the hub s ports are numbered in accordance with the way a Host will communicate with the ports 21h Table 3 3 Hub Configuration continued EEPROM OFFSET DESCRIPTION DEFAULT Bit 7 4 0000 Physical Port 2 is Disabled 00...

Page 27: ...ical port numbers assigned by the host Note The OEM must ensure that Contiguous Logical Port Numbers are used starting from 1 up to the maximum number of enabled ports this ensures that the hub s ports are numbered in accordance with the way a Host will communicate with the ports 43h Table 3 3 Hub Configuration continued EEPROM OFFSET DESCRIPTION DEFAULT Bit 7 4 0000 Physical Port 4 is Disabled 00...

Page 28: ...bit in Config Data Byte 3 Register CFG3 Format the hub s downstream port numbers can be remapped to different logical port numbers assigned by the host Note The OEM must ensure that Contiguous Logical Port Numbers are used starting from 1 up to the maximum number of enabled ports this ensures that the hub s ports are numbered in accordance with the way a Host will communicate with the ports 05h 39...

Page 29: ... High Speed Disable HS_DISABLE Disables the capability to attach as either a High Full Speed device and forces attachment as Full Speed only no High Speed support 0 High Full Speed 1 Full Speed Only High Speed disabled 0b 4 Multiple TT Enable MTT_ENABLE Enables one transaction translator per port operation Selects between a mode where only one transaction translator is available for all ports Sing...

Page 30: ...ally switched on and off on a port by port basis individual The ability to support power enabling on a port or ganged basis is hardware implementation dependent 0 Ganged switching all ports together 1 Individual port by port switching 1b Table 3 5 Config Data Byte 2 Register CFG2 Format BITS DESCRIPTION DEFAULT 7 6 RESERVED 00b 5 4 Over Current Timer OC_TIMER Over Current Timer delay 00 50ns 01 10...

Page 31: ...1 Port Re Map mode The mode enables remapping via the following EEPROM addresses EEPROM Address 36h Port Remap 12 EEPROM Address 37h Port Remap 34 EEPROM Address 38h Port Remap 5 0b 2 0 RESERVED 000b Table 3 7 Boost_Up Register BOOSTUP Format BITS DESCRIPTION DEFAULT 7 2 RESERVED 000000b 1 0 Upstream USB Electrical Signaling Drive Strength Boost Bit for Upstream Port A BOOST_IOUT_A 00 Normal elect...

Page 32: ...ectrical Signaling Drive Strength Boost Bit for Downstream Port 2 BOOST_IOUT_2 00 Normal electrical drive strength 01 Elevated electrical drive strength 4 boost 10 Elevated electrical drive strength 8 boost 11 Elevated electrical drive strength 12 boost 00b 1 0 RESERVED 00b Table 3 10 Status Command Register STCD Format BITS DESCRIPTION DEFAULT 7 2 RESERVED 000000b 1 Reset RESET Resets the interna...

Page 33: ... EEPROM controller will assume that the external Serial EEPROM is configured for auto loading If a value other than 0xA5 is read from the first address the EEPROM auto load will not commense Note The EEPROM contents are loaded for both the Hub and the Ethernet Controller as a result of a POR or nRESET The USB reset results only in the loading of the MAC address from the EEPROM A software reset SRS...

Page 34: ... 12 Dump of EEPROM Memory OFFSET BYTE VALUE 0000h A5 12 34 56 78 9A BC 01 0008h 04 05 09 04 0A 1D 00 00 0010h 00 00 00 00 00 00 12 22 0018h 12 2B 12 34 12 3D 00 00 0020h 24 04 14 95 00 01 9B 18 0028h 00 02 00 00 01 00 01 00 0030h 32 00 00 00 00 00 21 43 0038h 05 01 0A 03 53 00 4D 00 0040h 53 00 43 00 12 01 00 02 0048h FF 00 01 40 24 04 00 EC 0050h 00 01 01 00 00 01 09 02 0058h 27 00 01 01 00 E0 01...

Page 35: ...r Length 0 bytes NA 11h 00 Serial Number String Descriptor EEPROM Word Offset Don t Care 12h 00 Configuration String Descriptor Length 0 bytes NA 13h 00 Configuration String Descriptor Word Offset Don t Care 14h 00 Interface String Descriptor Length 0 bytes NA 15h 00 Interface String Descriptor Word Offset Don t Care 16h 12 Hi Speed Device Descriptor Length 18 bytes 17h 22h Hi Speed Device Descrip...

Page 36: ...ller Max Current Bus Register HCMCB 30h 32 Power on Time Register PWRT 31h 00 Boost_Up Register BOOSTUP 32h 00 Boost_7 5 Register BOOST75 33h 00 Boost_4 2 Register BOOST42 34h 00 RESERVED 35h 00 Port Swap Register PRTSP 36h 21 Port Remap 12 Register PRTR12 37h 43 Port Remap 34 Register PRTR34 38h 05 Port Remap 5 Register PRTR5 39h 01 Status Command Register STCD 3A 0A Size of Manufacturer ID Strin...

Page 37: ...aces 5Bh 01 Value to use as an argument to select this configuration 5Ch 00 Index of String Descriptor describing this configuration 5Dh E0 Self powered and remote wakeup enabled 5Eh 01 Maximum Power Consumption is 2 mA 5Fh 09 Size of Descriptor in Bytes 9 Bytes 60h 04 Descriptor Type Interface Descriptor 04h 61h 00 Number identifying this Interface 62h 00 Value used to select alternative setting ...

Page 38: ...h in bytes of data returned 0027h 39 bytes 7Eh 01 Number of Interfaces 7Fh 01 Value to use as an argument to select this configuration 80h 00 Index of String Descriptor describing this configuration 81h E0 Self powered and remote wakeup enabled 82h 01 Maximum Power Consumption is 2 mA 83h 09 Size of Full Speed Interface Descriptor in Bytes 9 Bytes 84h 04 Descriptor Type Interface Descriptor 04h 85...

Page 39: ...esult Some power supplies exhibit voltage spikes on their outputs when AC power is switched on or off In addition voltage transients on the AC power line may appear on the DC output If this possibility exists it is suggested that a clamp circuit be used Note 4 2 This rating does not apply to the following pins XI XO EXRES USBRBIAS Note 4 3 This rating does not apply to the following pins EXRES USB...

Page 40: ...ll values measured with maximum simultaneous traffic on the Ethernet port and all USB ports Note Magnetic power consumption 100BASE TX 42mA 10BASE T 104mA Table 4 1 Operational Current Consumption Power Dissipation VDD33IO VDD33A 3 3V PARAMETER MIN TYPICAL MAX UNIT 100BASE TX Full Duplex USB High Speed Supply current VDD33IO VDD33A 288 mA Power Dissipation Device Only 951 mW 10BASE T Full Duplex U...

Page 41: ...V V V mV uA pF Schmitt trigger Schmitt trigger Note 4 5 IS_5V Type Input Buffer Low Input Level High Input Level Negative Going Threshold Positive Going Threshold SchmittTrigger Hysteresis VIHT VILT Input Leakage VIN VSS or VDD33IO Input Leakage VIN 5 5V Input Capacitance VILI VIHI VILT VIHT VHYS IIH IIH CIN 0 3 1 01 1 39 345 10 1 18 1 6 420 5 5 1 35 1 8 485 10 120 3 5 V V V V mV uA uA pF Schmitt ...

Page 42: ...istive load Table 4 3 100BASE TX Transceiver Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Peak Differential Output Voltage High VPPH 950 1050 mVpk Note 4 8 Peak Differential Output Voltage Low VPPL 950 1050 mVpk Note 4 8 Signal Amplitude Symmetry VSS 98 102 Note 4 8 Signal Rise and Fall Time TRF 3 0 5 0 nS Note 4 8 Rise and Fall Symmetry TRFS 0 5 nS Note 4 8 Duty Cycle Distortion DCD 3...

Page 43: ...cation Refer to the Universal Serial Bus Revision 2 0 specification for detailed USB timing information 4 5 1 Equivalent Test Load Output timing specifications assume the 25pF equivalent test load illustrated in Figure 4 1 below 4 5 2 Reset Timing The nRESET pin input assertion time must be a minimum of 1 μS Assertion of nRESET is not a requirement However if used it must be asserted for the minim...

Page 44: ...s tcshckh EECS high before rising edge of EECLK 1070 ns tcklcsl EECLK falling edge to EECS low 30 ns tdvckh EEDO valid before rising edge of EECLK 550 ns tckhdis EEDO disable after rising edge EECLK 550 ns tdsckh EEDI setup to rising edge of EECLK 90 ns tdhckh EEDI hold after rising edge of EECLK 0 ns tckldis EECLK low to data disable OUTPUT 580 ns tcshdv EEDIO valid after EECS high VERIFY 600 ns ...

Page 45: ...ver Time is also referred to as Aging Note 4 14 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802 3u as 50 PPM Note 4 15 This number includes the pad the bond wire and the lead frame PCB capacitance is not included in this value The XO XI pin and PCB capacitance values are required to accurately calculate the value of the two external load capacitors These two extern...

Page 46: ... Table 5 1 LAN9514 64 QFN Dimensions MIN NOMINAL MAX REMARKS A 0 80 0 85 1 00 Overall Package Height A1 0 00 0 02 0 05 Standoff A2 0 65 0 80 Mold Cap Thickness D E 8 90 9 00 9 10 X Y Body Size D1 E1 8 65 8 75 8 85 X Y Mold Cap Size D2 E2 7 20 7 30 7 40 X Y Exposed Pad Size L 0 30 0 40 0 50 Terminal Length b 0 18 0 25 0 30 Terminal Width e 0 50 BSC Terminal Pitch K 0 35 Pin to Center Pad Clearance ...

Page 47: ...limeters unless otherwise noted 2 Dimension b applies to plated terminals and is measured between 0 15 and 0 30 mm from the terminal tip 3 Details of terminal 1 identifier are optional but must be located within the area indicated The terminal 1 identifier may be either a mold or marked feature Figure 5 2 LAN9514 Recommended PCB Land Pattern ...

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