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-44-
No. JXC
※
-OMT0002-C
8. Memory Map
8.1
Memory allocation
Table below shows the allocation of memory.
(1) PLC input port signals (from the controller to PLC)
Byte
Bit
7
6
5
4
3
2
1
0
0
AREA4
AREA3
AREA2
AREA1
BUSY4
BUSY3
BUSY2
BUSY1
1
ALARM4
ALARM3
ALARM2
ALARM1
INP4
INP3
INP2
INP1
2
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
3
ALARM
ESTOP
SVRE
INP
SETON
AREA
(OUT10)
BUSY
(OUT9)
OUT8
4 to 15
Reserve
(2) PLC output port signals (from the PLC to controller)
Byte
Bit
7
6
5
4
3
2
1
0
0
Reserve
1
Reserve
2
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
3
SVON
RESET
DRIVE
HOLD
SETUP
IN10
IN9
IN8
4 to 15
Reserve
8.2 Signals
(1) PLC input port signals (from the controller to PLC)
Signal name
Description
BUSY1
Busy signal for Axis X.
After the start of operation of the actuator, the signal is ON until the completion
time (theoretical value) passed, and then OFF when the operation is stopped
afterwards.
BUSY2
BUSY3
BUSY4
AREA1
Area signal for Axis 1
AREA2
Area signal for Axis 2
AREA3
Area signal for Axis 3
AREA4
Area signal for Axis 4
INP1
Positioning complete signal for Axis 1
INP2
Positioning complete signal for Axis 2
INP3
Positioning complete signal for Axis 3
INP4
Positioning complete signal for Axis 4
ALARM1
Alarm signal for Axis 1
Note1)
ALARM2
Alarm signal for Axis 2
Note1)
ALARM3
Alarm signal for Axis 3
Note1)
ALARM4
Alarm signal for Axis 4
Note1)
Note 1) Negative logic signal.