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MVME2502 Installation and Use (6806800R96L)

Functional Description

The JTAG board provides three different connectors for the ASSET hardware, flash
programming and the MVME2502 JTAG connector. The board is equipped with TTL buffers
to help improve the signal quality as it traverses over the wires.

4.20.3 Custom Debugging

Custom debugging makes use of the common on-chip processor. Refer to

Common On-

Chip Processor (COP) on page 78

for details.

Figure 4-4 JTAG Chain Diagram

Summary of Contents for MVME2502

Page 1: ...Penguin Edge MVME2502 Installation and Use P N 6806800R96L July 2022 ...

Page 2: ...another document as a URL to a SMART EC website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of SMART EC It is possible that this publication may contain reference to or information about SMART EC products programming or services that are not available in your country Such references or information must ...

Page 3: ...ing and Inspecting the Board 34 2 3 Requirements 34 2 3 1 Environmental Requirements 35 2 3 2 Power Requirements 36 2 3 3 Equipment Requirements 37 2 4 Configuring the Board 37 2 5 Installing Accessories 38 2 5 1 Rear Transition Module 38 2 5 2 PMC XMC Support 39 2 5 3 Installation of MVME2502 HDMNTKIT1 MVME2502 HDMNTKIT2 40 2 6 Installing and Removing the Board 43 2 7 Completing the Installation ...

Page 4: ...ctor XJ2 67 3 4 2 7 Miscellaneous P2020 Debug Connectors P4 67 3 5 Switches 68 3 5 1 Geographical Address Switch S1 68 3 5 2 SMT Configuration Switch S2 70 4 Functional Description 73 4 1 Block Diagram 73 4 2 Chipset 74 4 2 1 e500 Processor Core 74 4 2 2 Integrated Memory Controller 74 4 2 3 PCI Express Interface 75 4 2 4 Local Bus Controller LBC 75 4 2 5 Secure Digital Host Controller SDHC 75 4 2...

Page 5: ...1 PMC Add on Card 87 4 9 2 XMC Add on Card 87 4 10 SATA Interface 87 4 11 VME Support 87 4 11 1 Tsi148 VME Controller 88 4 12 USB 88 4 13 I2C Devices 88 4 14 Reset Control CPLD 89 4 15 Power Management 90 4 15 1 On board Voltage Supply Requirement 90 4 15 2 Power Up Sequencing Requirements 90 4 16 Clock Structure 91 4 17 Reset Structure 92 4 17 1 Reset Sequence 92 4 18 Thermal Management 92 4 19 R...

Page 6: ...rite Protect and I2 C Debug Register 107 5 5 13 PLD Test Register 1 108 5 5 14 PLD Test Register 2 109 5 5 15 PLD GPIO2 Interrupt Register 109 5 5 16 PLD Shutdown and Reset Control and Reset Reason Register 110 5 5 17 EMMC Reset Register 111 5 5 18 PLD Watchdog Timer Refresh Register 112 5 5 19 PLD Watchdog Control Register 112 5 5 20 PLD Watchdog Timer Count Register 113 5 5 21 PLD Watchdog Timer...

Page 7: ...terrupt Controller 133 7 4 I2 C Bus Device Addressing 134 7 5 Ethernet PHY Address 135 7 6 Other Software Considerations 135 7 6 1 MRAM 135 7 6 2 Real Time Clock 135 7 6 3 Quad UART 135 7 6 4 LBC Timing Parameters 136 7 7 Clock Distribution 137 7 7 1 System Clock 138 7 7 2 Real Time Clock Input 138 7 7 3 Local Bus Controller Clock Divisor 139 Replacing the Battery 141 A 1 Replacing the Battery 141...

Page 8: ...8 MVME2502 Installation and Use 6806800R96L Table of Contents ...

Page 9: ...t Panel LEDs Connectors and Switches 47 Figure 3 4 Front Panel LEDs 48 Figure 3 5 On board LEDs 50 Figure 3 6 Geographical Address Switch 69 Figure 3 7 SMT Configuration Switch Position 70 Figure 4 1 Block Diagram 73 Figure 4 2 SPI Device Multiplexing Logic 84 Figure 4 3 Clock Distribution Diagram 91 Figure 4 4 JTAG Chain Diagram 94 Figure 4 5 RTM Block Diagram 95 Figure A 1 Battery Location ENP1 ...

Page 10: ...List of Figures 10 MVME2502 Installation and Use 6806800R96L ...

Page 11: ...e 3 12 PMC J14 Connector 61 Table 3 13 JTAG Connector P6 63 Table 3 14 COP Header P50 64 Table 3 15 XMC Connector XJ1 Pin out 65 Table 3 16 XMC Connector XJ2 Pin out 67 Table 3 17 P2020 Debug Header P4 68 Table 3 18 Geographical Address Switch 69 Table 3 19 SMT Configuration Switch Settings 70 Table 4 1 P2020 GPIO Functions 76 Table 4 2 P2020 Strapping Options 78 Table 4 3 Ethernet Port Device Nam...

Page 12: ...d Reset Control and Reset Reason Register 111 Table 5 21 PLD Watchdog Timer Refresh Register 112 Table 5 22 PLD Watchdog Control Register 112 Table 5 23 PLD Watchdog Timer Count Register 113 Table 5 24 PLD Watchdog Timer Count Register 113 Table 5 25 Prescaler Register 114 Table 5 26 Control Registers 115 Table 5 27 Compare High Word Registers 116 Table 5 28 Compare Low Word Registers 116 Table 5 ...

Page 13: ...ew of the features of the product standard compliances mechanical data and ordering information Chapter 2 Hardware Preparation and Installation on page 33 outlines the installation requirements hardware accessories switch settings and installation procedures Chapter 3 Controls LEDs and Connectors on page 45 describes external interfaces of the board This includes connectors and LEDs Chapter 4 Func...

Page 14: ...ate Array GPIO General Purpose Input Output HDD Hard Disk Drive IEEE Institute of Electrical and Electronics Engineers LBC Local Bus Controller MCP Multi Chip Package MRAM Magnetoresistive Random Access Memory PCI Peripheral Component Interconnect PCI E PCI Express PCI X Peripheral Component Interconnect eXtended PIM PCI Mezzanine Card Input Output Module PLD Programmable Logic Device PMC PCI Mezz...

Page 15: ...ts are 0 and 1 bold Used to emphasize a word Screen Used for on screen output and code related elements or commands Sample of Programming used in a table 9pt Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File Exit Notation for selecting a submenu text Notation for variables and keys text Notati...

Page 16: ...ot avoided may result in minor or moderate injury Indicates a property damage message Indicates a hot surface that could result in moderate or serious injury Indicates an electrical situation that could result in moderate injury or death Indicates that when working in an ESD environment care should be taken to use proper ESD practices No danger encountered pay attention to important information No...

Page 17: ...s 6806800R96G September 2019 Re branded to SMART Embedded Computing template Updated Conventions table updated Freescale to NXP removed Ordering Information table added Ordering and Support Information updated RoHS compliance 6806800R96F May 2016 Removed Declaration of Conformity 6806800R96E April 2015 Updated Table B 1 6806800R96D December 2014 Updated Boot Options and Crisis Recovery 6806800R96C...

Page 18: ...18 MVME2502 Installation and Use 6806800R96L About this Manual About this Manual ...

Page 19: ...n this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal...

Page 20: ...fore touching the board or electronic components make sure that you are working in an ESD safe environment Board Malfunction Switches marked as reserved might carry production related functions and can cause the board to malfunction if their setting is changed Do not change settings of switches marked as reserved The setting of switches which are not marked as reserved has to be checked and change...

Page 21: ...an electric cable connected to a TPE bushing does not exceed 100 meters Make sure the TPE bushing of the system is connected only to safety extra low voltage circuits SELV circuits If in doubt ask your system administrator Battery Board System Damage Incorrect exchange of lithium batteries can result in a hazardous explosion When exchanging the on board lithium battery make sure that the new and t...

Page 22: ...nsufficient power the RTC is initialized Exchange the battery before seven years of actual battery use have elapsed PCB and Battery Holder Damage Removing the battery with a screw driver may damage the PCB or the battery holder To prevent damage do not use a screw driver to remove the battery from its holder ...

Page 23: ...tungen zu erfüllen Die Verwendung des Produkts in einer anderen Anwendung erfordert eine Sicherheitsüberprüfung für diese spezifische Anwendung Einbau Wartung und Betrieb dürfen nur von durch Penguin Solutions ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschließlich dazu das Wisse...

Page 24: ...quenzstrahlung im Rahmen der erlaubten Grenzwerte bewegt Warnung Dies ist eine Einrichtung der Klasse A Diese Einrichtung kann im Wohnbereich Funkstörungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Maßnahmen durchzuführen Betrieb Beschädigung des Produktes Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Produktes können zu Kurzschlüssen führen Betreiben S...

Page 25: ... von Zusatzmodulen Fehlerhafte Installation von Zusatzmodulen kann zur Beschädigung des Produktes und der Zusatzmodule führen Lesen Sie daher vor der Installation von Zusatzmodulen die zugehörige Dokumentation Kabel und Stecker Beschädigung des Produktes Bei den RJ 45 Steckern die sich an dem Produkt befinden handelt es sich entweder um Twisted Pair Ethernet TPE oder um E1 T1 J1 Stecker Beachten S...

Page 26: ... Zeiteinstellungen möglicherweise erhalten Datenverlust Wenn die Batterie wenig oder unzureichend mit Spannung versorgt wird wird der RTC initialisiert Tauschen Sie die Batterie aus bevor sieben Jahre tatsächlicher Nutzung vergangen sind Schäden an der Platine oder dem Batteriehalter Wenn Sie die Batterie mit einem Schraubendreher entfernen können die Platine oder der Batteriehalter beschädigt wer...

Page 27: ...rmance VME chassis environment with a 5 row backplane connector in the 2eVME or the 2eSST protocol mode The main features of the MVME2502 board are as follows NXP QorIQ P2020 based 6U form factor VME board 1000MHz to 1 2GHz core frequency 512KB L2 cache Three 10 100 1000 Mbps enhanced three speed Ethernet controllers eTSECs Two PCI E 1 0a x1 interface controller One PCI E 1 0a x2 interface control...

Page 28: ... RTM I2 C Presence Power Persistent data storage 512KB MRAM User Flash 8GB eMMC solid state storage Boot Flash 16 MB SPI Flash 2x 8MB Supports crisis recovery I2 C devices Real time clock Board temperature sensor 8 KB VPD EEPROM Two 64 KB User EEPROM MVME721E rear transition module I O Two Gigabit Ethernet interfaces PMC I O from PMC1 Operating system Based from BSP provided by NXP which is based ...

Page 29: ...3 Class A non residential EMC Directive 89 336 EEC EN55022 Class B EN55024 AS NZS CISPR 22 Class A EN300386 EMC requirements legal on system level predefined Penguin Solutions system ETSI EN 300 019 series Environmental Requirements Directive EU 2015 863 amending Annex II to Directive 2011 65 EU Directive on the restriction of the use of certain hazardous substances in electrical and electronic eq...

Page 30: ...ion or consult your local Penguin Solutions sales representative for the availability of other variants For technical assistance documentation or to report product damage or shortages contact your local Penguin Solutions sales representative or visit https www penguinsolutions com edge support 1 5 Product Identification The following figures show the location of the serial number label Figure 1 1 ...

Page 31: ...Introduction MVME2502 Installation and Use 6806800R96L 31 Figure 1 2 Serial Number Location ENP2 Variant ...

Page 32: ...32 MVME2502 Installation and Use 6806800R96L Introduction Introduction ...

Page 33: ...g the board Be sure to read the entire chapter including all caution and warning notes before you begin 1 Unpack the hardware Refer to Unpacking and Inspecting the Board on page 34 2 Configure the hardware by setting jumpers on the board and the RTM Refer to Configuring the Board on page 37 3 Install the rear transition module in the chassis Refer to Rear Transition Module on page 38 4 Install PMC...

Page 34: ...r differences to customer service 3 Remove the desiccant bag shipped together with the board and dispose of it according to your country s legislation 2 3 Requirements Make sure that the board meets the following requirements when operated in your particular system configuration NOTICE Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten ...

Page 35: ...ed Air 7CFM Operating Temperature 0 C to 55 C 40 C to 71 C Storage 40 C to 85 C 50 C to 100 C Vibration Sine 10min axis 2G 5 to 500Hz 5G 15 to 2000Hz Vibration Random 1hr axis 0 002g2 Hz 15 to 2000Hz 2GRMS 0 04g2 Hz 15 to 2000Hz 8GRMS 1 1 Flat 15 1000Hz 6db octave 1000Hz 2000Hz MIL STD 810F Figure 514 5C 17 Shock 20g 11mS 30g 11mS Humidity to 95 RH non condensing to 95 RH non condensing to 100 RH ...

Page 36: ...ions The following table provides an estimate of the typical and maximum power required The following table shows the power available when the MVME2502 is installed in either a three row or five row chassis and when PMCs are present Table 2 2 Power Requirements Board Variant Maximum Calculated Typical Measured Operating MVME2502 02120201E 28 93W 21 8 MVME2502 02120201S 28 93W 21 8 MVME2502 0210020...

Page 37: ...em and or application software Transition module and connecting cables 2 4 Configuring the Board The board provides software control over most options Settings can be modified to fit the user s specifications To configure set the bits in the control register after installing the board in a system Make sure that all user defined switches are properly set before installing a PMC XMC module For more ...

Page 38: ... 6 Slide the transition module into the chassis until resistance is felt 7 Move the injector ejector levers in an inward direction 8 Verify that the transition module is properly seated and secure it to the chassis using two screws adjacent to the injector ejector levers NOTICE Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life...

Page 39: ...eboard 1 Attach an ESD strap to your wrist Attach the other end of the strap to the chassis as a ground Make sure that it is securely fastened throughout the procedure 2 Remove the PMC XMC filler plate from the front panel cut out 3 Slide the front bezel of the PMC XMC into the front panel cut out from backside The front bezel of the PMC XMC module will be placed with the board when the connectors...

Page 40: ...n the screws 6 Install the board into the appropriate card slot Make sure that the board is well seated into the backplane connectors Do not damage or bend connector pins 7 Replace the chassis or system cover 8 Reconnect the system to the power source and then turn on the system 2 5 3 Installation of MVME2502 HDMNTKIT1 MVME2502 HDMNTKIT2 Installation Procedure 1 Attach washers and hex standoffs to...

Page 41: ...6800R96L 41 2 Assemble the SATA adapter board to the blade and ensure that it is properly aligned with the standoff Attach the screws to anchor the SATA adapter board to the blade NOTE The 3 3V key must be removed to install the SATA kit 3 Attach hex standoff to main board ...

Page 42: ...42 MVME2502 Installation and Use 6806800R96L Hardware Preparation and Installation Hardware Preparation and Installation 4 Attach HDD with interface PCB to main board using screws as shown below ...

Page 43: ...rd position 5 Slide the board into the chassis until resistance is felt 6 Simultaneously move the injector ejector levers in an inward direction 7 Verify that the board is properly seated and secure it to the chassis using the two screws located adjacent to the injector ejector levers 8 Connect the appropriate cables to the board Removal Procedure 1 Turn off the power 2 Disconnect all the cables 3...

Page 44: ...tings for the MVME2502 are Eight bits per character One stop bit per character Parity disabled no parity Baud rate of 9600 baud Verify that hardware is installed and the power peripheral cables connected are appropriate for your system configuration Replace the chassis or system cover reconnect the chassis to power source and turn the equipment power on NOTICE Product Damage RJ 45 connectors on mo...

Page 45: ...2 Installation and Use 6806800R96L 45 Chapter 3 Controls LEDs and Connectors 3 1 Board Layout The following figure shows the components and connectors on the MVME2502 board Figure 3 1 Board Layout ENP1 Variant ...

Page 46: ...46 MVME2502 Installation and Use 6806800R96L Controls LEDs and Connectors Controls LEDs and Connectors Figure 3 2 Board Layout ENP2 Variant ...

Page 47: ...e 6806800R96L 47 3 2 Front Panel The following components are found on the MVME2502 ENP1 and ENP2 front panel Figure 3 3 Front Panel LEDs Connectors and Switches PMC XMC 1 SPEED SPEED eTSEC 1 eTSEC 2 PMC XMC 2 USER 1 RESET FAIL SERIAL USB ACT ACT PORT SWITCH ...

Page 48: ...VME2502 is the VMEbus system controller 3 3 LEDs The MVME2502 utilize light emitting diodes LEDs to provide a visible status indicator on the front panel These LEDs show power failures power up states Ethernet link speed Ethernet activity SATA link and activity and PCIe valid lane status There are few user configurable LEDs Each LED description is necessary for troubleshooting and debugging 3 3 1 ...

Page 49: ...C2 Link Speed Front panel Integrated RJ 45 LED Off Amber Green No link 10 100BASE T operation 1000 BASE T operation GENET1 ACT eTSEC2 Activity Front panel Integrated RJ 45 LED Off Blinking Green No activity Activity proportional to bandwidth utilization GENET2 SPEED eTSEC1 Link Speed Front panel Integrated RJ 45 LED Left Off Amber Green No link 10 100BASE T operation 1000BASE T operation GENET2 AC...

Page 50: ...ction Color Description D9 Power Fail Red This indicator is illuminated when one or more of the on board voltage rails fails D33 User Defined Amber Controlled by the CPLD Used for boot up sequence indicator D34 User Defined Amber Controlled by the CPLD Used for boot up sequence indicator D35 User Defined Amber Controlled by the CPLD Used for boot up sequence indicator D36 Early Power Fail Amber Th...

Page 51: ... the MVME2502 board These connectors are divided between the front panel connectors and the backplane connectors The front panel connectors include the J1 and the J5 connectors The backplane connectors include the P1 and the P2 connectors 3 4 1 1 RJ 45 with Integrated Magnetics The MVME2502 uses an X2 RJ 45 Table 3 3 Ethernet Tri Speed RJ 45 Connectors GENET1 and GENET2 Pin Name Signal Description...

Page 52: ... panel connector A male to male micro mini DB9 adapter cable is available under Penguin Edge part number SERIAL MINI D 30 W2400E01A The pin assignments for these connectors are as follows 3 4 1 3 USB Connector The MVME2502 uses upright USB receptacle mounted in the front panel Table 3 4 Front Panel Serial Port Pin Signal Description 1 NC 2 RX 3 TX 4 NC 5 GND 6 NC 7 RTS 8 CTS 9 NC Table 3 5 USB Con...

Page 53: ...TA 9 GND GND 3 DATA 2 ACFAIL DATA 10 NC NC 4 DATA 3 BGIN0 DATA 11 NC GND 5 DATA 4 BGOUT0 DATA 12 NC NC 6 DATA 5 BGIN1 DATA 13 NC GND 7 DATA 6 BGOUT1 DATA 14 NC NC 8 DATA 7 BGIN2 DATA 15 NC GND 9 GND BGOUT2 GND GAP NC 10 SYSCLK BGIN3 SYSFAIL GA0 GND 11 GND BGOUT3 BERR GA1 NC 12 DS1 BR0 SYSRESET 3 3V not used GND 13 DS0 BR1 LWORD GA2 NC 14 WRITE BR2 AM 5 3 3V not used GND 15 GND BR3 ADD 23 GA3 NC 16...

Page 54: ...7 IRQ7 ADD 32 3 3V not used GND 25 ADD 6 IRQ6 ADD 33 NC NC 26 ADD 5 IRQ5 ADD 34 3 3V not used GND 27 ADD 4 IRQ4 ADD 35 NC NC 28 ADD 3 IRQ3 ADD 36 3 3V not used GND 29 ADD 2 IRQ2 ADD 37 NC NC 30 ADD 1 IRQ1 ADD 38 3 3V not used GND 31 12V NC 12V 12V NC 32 5V 5V 5V 5V GND Table 3 6 VMEbus P1 Connector continued Pin Row A Row B Row C Row D Row Z Table 3 7 VMEbus P2 Connector Pin Row A Row B Row C Row ...

Page 55: ...C IO 34 DATA 19 PMC IO 33 GE4_LINK_LED Serial 3 RX 18 PMC IO 36 DATA 20 PMC IO 35 GE4_A_LED GND 19 PMC IO 38 DATA 21 PMC IO 37 GND Serial 3 TX 20 PMC IO 40 DATA 22 PMC IO 39 GE4_3 GND 21 PMC IO 42 DATA 23 PMC IO 41 GE4_3 Serial 3 CTS 22 PMC IO 44 GND PMC IO 43 GND GND 23 PMC IO 46 DATA 24 PMC IO 45 GE4_2 Serial 3 RTS 24 PMC IO 48 DATA 25 PMC IO 47 GE4_2 GND 25 PMC IO 50 DATA 26 PMC IO 49 GND Seria...

Page 56: ... 31 PMC IO 62 GND PMC IO 61 GND Serial 4 RTS 32 PMC IO 64 5V PMC IO 63 5V GND Table 3 7 VMEbus P2 Connector continued Pin Row A Row B Row C Row D Row Z Table 3 8 Custom SATA Connector J3 Pin Signal Description Pin Signal Description 1 GND 21 GND 2 GND 22 SATA POWER ENABLE 3 NC 23 NC 4 SATA TX 24 SATA DETECT 5 NC 25 NC 6 SATA TX 26 GND 7 GND 27 NC 8 GND 28 GND 9 GND 29 GND 10 GND 30 GND 11 NC 31 3 ...

Page 57: ... 1 for the location of the PMC connectors 16 GND 36 5V 17 NC 37 3 3V 18 GND 38 5V 19 NC 39 3 3V 20 GND 40 5V Table 3 8 Custom SATA Connector J3 continued Pin Signal Description Pin Signal Description Table 3 9 PMC J11 J111 Connector Pin Signal Description Pin Signal Description 1 JTAG TCK 33 FRAME 2 12V 34 GND 3 GND 35 GND 4 INT A 36 IRDY 5 INT B 37 DEVSEL 6 INT C 38 5V 7 PRESENT SIGNAL 39 PCIXCAP...

Page 58: ... AD 11 17 REQ A 49 AD 9 18 5V 50 5V 19 3 3V 51 GND 20 AD 31 52 CBE0 21 AD 28 53 AD 6 22 AD 27 54 AD 5 23 AD 25 55 AD 4 24 GND 56 GND 25 GND 57 3 3V 26 CBE3 58 AD 3 27 AD 22 59 AD 2 28 AD 21 60 AD 1 29 AD 19 61 AD 0 30 5V 62 5V 31 3 3V 63 GND 32 AD 17 64 REQ64 Table 3 9 PMC J11 J111 Connector continued Pin Signal Description Pin Signal Description ...

Page 59: ...SELB 3 JTAG TMS 35 TRDY 4 JTAG TDO 36 3 3V 5 JTAG TDI 37 GND 6 GND 38 STOP 7 GND 39 PERR 8 NC 40 GND 9 NC 41 3 3V 10 NC 42 SERR 11 BUSMODE2 Pulled UP 43 CBE1 12 3 3V 44 GND 13 PCI RESET 45 AD 14 14 BUSMODE3 PULLED DWN 46 AD 13 15 3 3V 47 M66EN 16 BUSMODE4 PULLED DWN 48 AD 10 17 NC 49 AD 8 18 GND 50 3 3V 19 AD 30 51 AD 7 20 AD 29 52 REQB 21 GND 53 3 3V 22 AD 26 54 GNTB 23 AD 24 55 NC ...

Page 60: ...K64 30 GND 62 3 3V 31 AD 16 63 GND 32 CBE2 64 NC Table 3 10 PMC J12 J222 Connector continued Pin Signal Description Pin Signal Description Table 3 11 PMC J13 J333 Connector Pin Signal Description Pin Signal Description 1 NC 33 GND 2 GND 34 AD48 3 GND 35 AD 47 4 CBE7 36 AD 52 5 CBE6 37 AD 45 6 CBE5 38 GND 7 CBE4 39 3 3V 8 GND 40 AD 40 9 3 3V 41 AD 43 10 PAR64 42 AD 42 11 3 3V 43 AD 41 12 AD 62 44 G...

Page 61: ...20 GND 52 AD 36 21 3 3V 53 AD 35 22 AD 56 54 AD 34 23 AD 55 55 AD 33 24 AD 54 56 GND 25 AD 53 57 3 3V 26 GND 58 AD 32 27 GND 59 NC 28 GND 60 NC 29 AD 51 61 NC 30 AD 50 62 GND 31 AD 49 63 GND 32 GND 64 NC Table 3 11 PMC J13 J333 Connector continued Pin Signal Description Pin Signal Description Table 3 12 PMC J14 Connector Pin Signal Description Pin Signal Description 1 PMC IO 1 33 PMC IO 33 ...

Page 62: ... PMC IO 10 42 PMC IO 42 11 PMC IO 11 43 PMC IO 43 12 PMC IO 12 44 PMC IO 44 13 PMC IO 13 45 PMC IO 45 14 PMC IO 14 46 PMC IO 46 15 PMC IO 15 47 PMC IO 47 16 PMC IO 16 48 PMC IO 48 17 PMC IO 17 49 PMC IO 49 18 PMC IO 18 50 PMC IO 50 19 PMC IO 19 51 PMC IO 51 20 PMC IO 20 52 PMC IO 52 21 PMC IO 21 53 PMC IO 53 22 PMC IO 22 54 PMC IO 54 23 PMC IO 23 55 PMC IO 55 24 PMC IO 24 56 PMC IO 56 25 PMC IO 25...

Page 63: ... PMC IO 30 62 PMC IO 62 31 PMC IO 31 63 PMC IO 63 32 PMC IO 32 64 PMC IO 64 Table 3 12 PMC J14 Connector continued Pin Signal Description Pin Signal Description Table 3 13 JTAG Connector P6 Pin Signal Description Pin Signal Description 1 NC 2 3 3V FROM 5V 3 SPI HOLD 0 4 SPI CS 0 5 SPI CLK 6 SPI CS 1 7 SPI HOLD 1 8 SPI MOSI 9 SPI MISO 10 GND 11 SPI VCC 12 SCAN 1 TCK 13 SCAN 1 TDI 14 GND 15 SCAN 1 T...

Page 64: ...3 TDO 34 SCAN 3 TCK 2 35 2 5V 36 SCAN 3 TCK 3 37 SCAN 3 TDI 38 GND 39 SCAN 3 TRST 40 SCAN 3 TCK3 41 SCAN 4 TCK 1 42 SCAN 4 TMS 43 GND 44 SCAN 4 TDO 45 SCAN 4 TCK 2 46 3 3V 47 GND 48 SCAN 4 TDI 49 SCAN 4 TCK 3 50 SCAN 4 TRST 51 SCAN 5 TMS 52 SCAN 5 53 SCAN 5 TDO 54 GND 55 3 3V 56 SCAN5 TCK2 57 SCAN 5 TDI 58 GND 59 SCAN 5 TRST 60 NC Table 3 13 JTAG Connector P6 continued Pin Signal Description Pin S...

Page 65: ...OP RUNSTOP Pulled UP 6 COP VDD SENSE 7 JTAG TCK 8 COP CHECK STOP IN 9 JTAG TMS 10 NC 11 P2020 SW RESET 12 COP PRESENT 13 COP HARD RESET 14 KEYING 15 COP CHECK STOP OUT 16 GND Table 3 14 COP Header P50 continued Pin Signal Description Table 3 15 XMC Connector XJ1 Pin out Pin Row A Row B Row C Row D Row E Row F 1 RX0 RX0 3 3V NC NC 3 3V 2 GND GND JTAG TRST GND GND HRESET 3 NC NC 3 3V NC NC 3 3V 4 GN...

Page 66: ...C NC NC 3 3V 10 GND GND JTAG TDO GND GND GA 0 11 TX0 TX0 BIST PULLED UP NC NC 3 3V 12 GND GND GA 1 GND GND PRESENT 13 NC NC NC NC NC 3 3V 14 GND GND GA 2 GND GND I2C DATA 15 NC NC NC NC NC 3 3V 16 GND GND MVMRO PULLED DOWN GND GND I2C CLOCK 17 NC NC NC NC NC NC 18 GND GND NC GND GND NC 19 CLK CLK NC ROOT 0 PULLED UP ROOT0 PULLED UP NC Table 3 15 XMC Connector XJ1 Pin out continued Pin Row A Row B ...

Page 67: ... RX0 3 3V RX1 RX1 3 3V 2 GND GND JTAG TRST GND GND HRESET 3 NC NC 3 3V NC NC 3 3V 4 GND GND JTAG TCK GND GND MRSTO PULLED UP 5 NC NC 3 3V NC NC 3 3V 6 GND GND JTAG TMS GND GND 12V 7 NC NC 3 3V NC NC 3 3V 8 GND GND JTAG TMS GND GND 12V 9 NC NC NC NC NC 3 3V 10 GND GND JTAG TDO GND GND GA 0 11 TX0 TX0 BIST PULLED UP TX1 TX1 3 3V 12 GND GND GA 1 GND GND PRESENT 13 NC NC NC NC NC 3 3V 14 GND GND GA 2 ...

Page 68: ...he five row backplane can use the geographical address switch to assign a geographical address based on the following diagram Table 3 17 P2020 Debug Header P4 Pin Signal Description 1 MSRCDI0 2 GND 3 MSRCDI1 4 MDVAL 5 MSRCDI2 6 TRIG_OUT 7 MSRCDI3 8 TRIG_IN 9 MSRCID4 10 GND NOTICE Board Malfunction Switches marked as reserved might carry production related functions and can cause the board to malfu...

Page 69: ...switches Figure 3 6 Geographical Address Switch Table 3 18 Geographical Address Switch Position Function Default S1 1 VME SCON Auto1 Auto SCON S1 2 VME SCON SEL2 Non SCON S1 3 GAP 1 S1 4 GA4 1 S1 5 GA3 1 S1 6 GA2 1 S1 7 GA1 1 S1 8 GA0 1 1 The VME SCON MAN switch is OFF to select Auto SCON mode The switch is ON to select manual SCON mode which works in conjunction with the VME SCON SEL switch 2 The...

Page 70: ...default setting on all switch positions is OFF and is indicated by brackets in Table 3 1 Figure 3 7 SMT Configuration Switch Position Table 3 19 SMT Configuration Switch Settings SW2 DEFAULT Signal Name Description Notes 1 OFF Normal Env NORMAL_ENV Safe Start ON Use normal ENV OFF Use safe ENV 2 OFF Flash Block A BOOT_BLOCK _A Boot Block B Select 3 OFF WP disabled FLASH_WP_N Flash Write Protect 4 ...

Page 71: ...is switch can be configured to run either 100 MHz or 133MHz frequency 6 OFF WP Enabled MASTER_WP_ DISABLED The on board EEPROM can be write protected via S2 6 switching it ON will disable the write protection For I2C write protect only 7 OFF Front GBE_MUX_ SEL User Defined switch that will select if the GBE PHY will function on the front panel or on the Back PLANE 8 OFF CPU Reset Deasserted Reserv...

Page 72: ...72 MVME2502 Installation and Use 6806800R96L Controls LEDs and Connectors Controls LEDs and Connectors ...

Page 73: ...All variants provide front panel access to one serial port via a micro mini DB 9 connector two 10 100 1000 Ethernet port one is configurable to be routed to the front panel or the rear panel through a RJ 45 connector and one TypeA USB Port It includes Board Fail LED indicator user defined LED indicator and a ABORT RESET switch Figure 4 1 Block Diagram ...

Page 74: ...dual core It operates from 1 0GHz up to 1 2GHz core frequency The e500 processor core is a low power implementation of the family of reduced instruction set computing RISC embedded processor that implement the Book E definition of the PowerPC architecture The e500 is a 32 bit implementation of the Book E architecture using the lower words of 64 bit general purpose registers GPRs while E500v2 uses ...

Page 75: ...The P2020 has options for up to three PCIe interfaces with up to x4 link width The PCIe controller is configured to operate as either PCIe root complex RC or as an endpoint EP device 4 2 4 Local Bus Controller LBC The main component of the enhanced LBC is the memory controller that provides a 16 bit interface to various types of memory devices and peripherals The memory controller is responsible f...

Page 76: ... speed DMA channels all of which are capable of complex data movement and advanced transaction chaining 4 2 10 Enhanced Three Speed Ethernet Controller eTSEC The eTSEC controller of the device communicates to10Mbps 100Mbps and 1Gbps Ethernet IEE 802 3 networks and devices featuring generic 8 to 16 bit FIFO ports The MVME2502 uses the eTSEC using the RGMII interface 4 2 11 General Purpose I O GPIO ...

Page 77: ...9 Connected to pin T6 of the CPLD unused input 05 R24 Connected to pin R6 of the CPLD unused input 04 U29 Connected to INTA of the QUART Programmed as a discrete input or to generate IRQ11 Also connected to pin P16 of the CPLD unused input 03 N24 Connected to pin P15of the CPLD 02 P29 Connected to Pin R16 of the CPLD Programmed to generate a IRQ09 interrupt to the CPU based on contents of the CPLD...

Page 78: ...he MVME2502 Table 4 2 P2020 Strapping Options Functional Signal Name Reset Configuration Name Config Resistor Options Default Value Description LA 29 31 cfg_sys_pii 0 2 Yes 000 4 1 ratio CCB clock SYSCLK 100MHz CCB 400Mhz TSEC_1588_CLKOUT TSEC_1588_PULSE_ OUT1 TSEC_1588_PULSE_ OUT2 cfg_ddr_pii 0 2 Yes 011 8 1 ratio DDRCLK 100MHz DDRPLL data rate 800MHz LBCTL LALE LGPL2 LOE LFRE cfg_core0pii 0 2 Ye...

Page 79: ...II protocol TSEC1_TXD 3 1 TSEC2_TX_ERR cfg_io_ports 0 3 Yes 0010 PCIE1 1x PCIE2 1x PCI3 2x MSRCID0 cfg_elbc_ecc Yes 0 eLBC ECC checking is disabled LA28 cfg_sys_speed Yes 1 SYSCLK is at or above 66MHz default LA23 cfg_plat_speed Yes 1 Platform clock is at or above 333MHz default LA24 cfg_core0_speed Yes 1 ENP1 Core0 clock frequency is greater than 1000MHz 0 ENP2 Core0 clock frequency is less than ...

Page 80: ...ons provided They are only listed for reference LGPL1 cfg_sgmii2 No 1 eTSEC2 interface operates in parallel interface mode default TSEC_1588_ALARM_ OUT2 cfg_sgmii3 No 1 eTSEC3 interface operates in parallel interface mode default TSEC_1588_ALARM_ OUT1 cfg_srds_refclk No 1 100MHz SERDES ref clock for PCIE default LWE1 LBS1 LA 18 19 cfg_host_agt 0 2 No 111 Processor acts as the host root complex for...

Page 81: ...inutes hours day date month year accurately The INT_A pin of the DS1337 is connected to the CPU GPIO 1 pin to allow the DS1337 to generate interrupts to the CPU Access to the DS1337 is provided via the I2 C port 0 from the CPU and responds to a base I2 C address of D0 The MVME2502 provides a socketed 190mAh primary battery to power the RTC when the module is out of service 4 4 2 P2020 Internal Tim...

Page 82: ...rated speed and activity status indicator LEDs Isolation transformers are provided on the board for each port 4 6 SPI Bus Interface The enhanced serial peripheral interface eSPI allows the device to exchange data with peripheral devices such as EEPROMs RTC Flash and the like The eSPI is a full duplex synchronous character oriented channel that supports a simple interface such as receive transmit c...

Page 83: ...e with DediProg SPI Universal Pin Header Using 60 pin external JTAG header An external JTAG board with a JTAG multiplexer is compatible with the MVME2502 and is attached using an external cable It is used to update the boot loader in the field Using this method programming is done through the JTAG interface or by using the dedicated SPI Flash programming header on the JTAG board Factory Pre Progra...

Page 84: ...the software can perform read write processes on any SPI device including copying from one SPI device to another With this flexible approach to firmware redundancy one should always be able to recover from a corrupt active firmware image as long as a healthy firmware image is maintained in single bootable SPI Device The MVME2502 supports automatic switch over If booting one device is not successfu...

Page 85: ...r Penguin Edge Part Number SERIAL MINI D 30 W2400E01A and is approximately 12 inches in length Only 115200bps and 9600bps are supported The default baud rate on the front panel serial is 9600kbps 4 8 Rear UART Control The MVME2502 utilizes the Exar ST16C554 quad UART QUART to provide four asynchronous serial interface to the RTM These devices feature 16 bytes of transmit and receive first in first...

Page 86: ...the 3 3 V PMC keying position in order to be populated on the MVME2502 board The XMC specification accommodates this since it is expected that carrier cards will host both XMC and PMC capable add on cards The MVME2502 have a keying pin at the 3 3V location at each PMC site The MVME2502 boards are not 5 volt PMC IO compatible The MVME2502 also has a 5 volt keying pin location at each PMC site At PM...

Page 87: ...s not provide 12V to the XMC VPWR pins Voltage tolerances for VPWR and all carrier supplied voltage 3 3V 12V 12V are defined by the base XMC standard 4 10 SATA Interface The MVME2502 supports an optional 2 5 SATA HDD The connector interface is compatible with the SATAMNKIT which contains the following one SSD HDD one SATA board screws and a mounting guide The SATA connector supports a horizontal m...

Page 88: ... 2 0 compliant serial interface engine DC power to the front panel USB port is supplied using a USB power switch which provides soft start current limiting over current detection and power enable for port 1 4 13 I2C Devices The MVME2502 utilizes two I2 C ports provided by the board s processor The I2 C bus is a two wire serial data SDA and serial clock SCL synchronous multi master bi directional s...

Page 89: ...oder and LED controller Table 4 4 P2020 I2 C Port1 Devices Ref Designator I2 C Device I2 C 8 bit Base Address Device Type U39 Temperature Sensor 98 ADT 7461 Temperature Sensor U37 SPD A0 AT24C02 256x8 U40 VPD EEPROM A8 AT24C64 8192x8 U4 RTM AA Reserved for RTM U43 User EEPROM 1 AC AT24C512 65536x8 U45 User EEPROM 2 AE AT24C512 65536x8 U42 RTC D0 DS 1337 real time clock U6 IDT Clocking Chip DC IDT ...

Page 90: ...hassis power switch must be power cycled 4 15 1 On board Voltage Supply Requirement The on board power supply is considered to be out of regulation if the output voltage level is below the minimum required power or goes beyond the maximum 4 15 2 Power Up Sequencing Requirements The power up sequence describes the voltage rail power up timing which is designed to support all the chip supply voltage...

Page 91: ...tion MVME2502 Installation and Use 6806800R96L 91 4 16 Clock Structure A total of three IDT chips a discrete oscillator and crystal to support all the clock requirements of MVME2502 Figure 4 3 Clock Distribution Diagram ...

Page 92: ...re sensor is located near the processor The CPU temperature sensor is located on the processor The MVME2502 thermal management support will interrupt the process only to show the current board and CPU temperature This interrupt is routed directly to one of the processor s IRQ4 The table below shows the low and high threshold temperature in order for the interrupt to be asserted 4 19 Real Time Cloc...

Page 93: ...ME2502 provides a 60 pin header that connects to the JTAG board via customize cable The JTAG bypass will connect when no XMC or PMC is connected to its corresponding locations Once an external XMC or PMC is unmounted its corresponding JTAG bypass will close to complete the JTAG chain Table 4 8 POST Code Indicator on the LED Sequence D33 D34 D35 Description 1 Off Off Off U boot has been copied from...

Page 94: ...the ASSET hardware flash programming and the MVME2502 JTAG connector The board is equipped with TTL buffers to help improve the signal quality as it traverses over the wires 4 20 3 Custom Debugging Custom debugging makes use of the common on chip processor Refer to Common On Chip Processor COP on page 78 for details Figure 4 4 JTAG Chain Diagram ...

Page 95: ...cts directly to the VME backplane in chassis with an 80 mm deep rear transition area It has the following features Figure 4 5 RTM Block Diagram Table 4 9 Transition Module Features Function Features I O One five row P2 backplane connector for serial and Ethernet I O passed from the MVME2502 Four RJ 45 connectors for rear panel I O four asynchronous serial channels Two RJ 45 connectors with integra...

Page 96: ...96 MVME2502 Installation and Use 6806800R96L Functional Description Functional Description ...

Page 97: ...ress Map Device Name Start Address End Address Size DDR 0x0000_0000 0x7fff_ffff 2GB PCIE 3 Mem 0x8000_0000 0x9fff_ffff 512MB PCIE 2 Mem 0xa000_0000 0xbfff_ffff 512MB PCIE 1 Mem 0xc000_0000 0xdfff_ffff 512MB PCIE 3 IO 0xffc0_0000 0xffc0_ffff 64KB PCIE 2 IO 0xffc1_0000 0xffc1_ffff 64KB PCIE 1 IO 0xffc2_0000 0xffc2_ffff 64KB UART0 0xffc4_0000 0xffc4_ffff 64KB UART1 0xffc5_0000 0xffc5_ffff 64KB UART2 ...

Page 98: ...009ffff ENV Variables 0x00100000 0x0011ffff Available Flash 0x00120000 0x007fffff Table 5 3 Linux Devices Memory Map Device Memory Range Memory Area Size Ram Mem 0x00000000 0x7fffffff 2GB PCIE3 Mem 0x80000000 0x9fffffff 512MB PCIE2 Mem 0xa0000000 0xbfffffff 512MB PCIE1 Mem 0xc0000000 0xdfffffff 512MB MRAM 0xfff00000 0xfff7ffff 512KB PCIE3 IO 0xffc00000 0xffc0fff 64KB PCIE2 IO 0xffc10000 0xffc1ffff...

Page 99: ...xffe05000 0xffe05fff 4KB SPI CCSR 0xffe07000 0xffe07fff 4KB PCIE3 CCSR 0xffe08000 0xffe08fff 4KB PCIE2 CCSR 0xffe09000 0xffe09fff 4KB PCIE1CCSR 0xffe0a000 0xffe0afff 4KB DMA2 CCSR 0xffe0c100 0xffe0c303 516B GPIO CCSR 0xffe0fc00 0xffe0fcff 256B L2 Cache CCSR 0xffe20000 0xffe20fff 4KB DMA1 CCSR 0xffe21100 0xffe21303 516B USB CCSR 0xffe22000 0xffe22fff 4KB ETSEC1 CCSR 0xffe24000 0xffe24fff 4KB ETSEC2...

Page 100: ...ld year of the timers registers PLD msi CCSR 0xffe41600 0xffe4167f 128B mpic CCSR 0xffe40000 0xffe7ffff 256KB Global Utilities CCSR 0xffee0000 0xffee0fff 4KB L2 Cache Mem 0xf0f80000 0xf0ffffff 512KB Table 5 3 Linux Devices Memory Map continued Device Memory Range Memory Area Size Table 5 4 PLD Revision Register REG PLD Revision Register 0xFFDF0000 Bit 7 6 5 4 3 2 1 0 Field PLD_REV OPER R RESET 0x0...

Page 101: ... The MVME2502 PLD provides an 8 bit register which contains the build day of the timers registers PLD Field PLD_REV OPER R RESET 0x12 Table 5 5 PLD Year Register REG PLD Year Register 0xFFDF0004 Table 5 6 PLD Month Register REG PLD Year Register 0xFFDF0005 Bit 7 6 5 4 3 2 1 0 Field PLD_REV OPER R RESET 0x11 Table 5 7 PLD Day Register REG PLD Revision Register 0xFFDF0006 Bit 7 6 5 4 3 2 1 0 Field P...

Page 102: ...egister REG PLD Revision Register 0xFFDF0007 Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Field PLD_REV OPER R RESET 0x00 Table 5 9 PLD Power Good Monitor Register REG PLD PWRDG_MNTR 0xFFDF0012 Bit 7 6 5 4 3 2 1 0 Field RSVD PWR_V1 P05_PW RGD PWR_V1 P2_PWR GD PWR_V1 P8_PWR GD PWR_V3 P3_PWR GD PWR_V2 P5_PWR GD PWR_V1 P2_SW_ PWRGD PWR_V1 P5_PWR GD OPER R RESET 0 0 0 0 0 0 0 0 Field Description PWR_V1P05_...

Page 103: ... the status of the PCI PMC XMC interface signals PWR_V1P2_SW_PWRGD 1 2V SW Supply power good indicator PWR_V1P5_PWRGD 1 5V Supply power good indicator 1 Supply Good and Stable 0 Otherwise Table 5 10 PLD LED Control Register REG PLD LED_CTRL 0xFFDF001C Bit 7 6 5 4 3 2 1 0 Field D1 D35 D34 D33 D38 D37 D2 Red D2 Yellow OPER R W RESET 1 0 0 0 0 0 0 0 Table 5 11 PLD PCI PMC XMC Slot1 Monitor Register R...

Page 104: ...pen default PMC1_EREADY Indicates PCI device is ready for enumeration 1 PMC ready for enumeration 0 PMC is not ready for enumeration PMC1P_N PMC Presence Indicator 1 PMC is not present 0 PMC is present XMCP1_N XMC Presence Indicator 1 XMC is not present 0 XMC is present PCI1_PCIXCAP PCI Capability Indicator 1 PCI X capable 0 PCI capable Table 5 12 PLD PCI PMC XMC Slot2 Monitor Register REG PLD PCI...

Page 105: ...2 4 open default PMC2_EREADY Indicates PCI device is ready for enumeration 1 PMC ready for enumeration 0 PMC is not ready for enumeration SATA0_DETECT_N SATA drive presence indicator 1 SATA not present 0 SATA present PMC2P_N PMC Presence Indicator 1 PMC is not present 0 PMC is present XMCP2_N XMC Presence Indicator 1 XMC is not present 0 XMC is present PMC2_PCIXCAP PCI Capability Indicator 1 PCI X...

Page 106: ...N Pin out 1 No TSI Fail 0 TSI Fail NORMAL_ENV Normal Environment Switch Indicator 1 Use safe ENV 0 Use normal ENV SCON System Controller Indicator 1 System Controller 0 Non system Controller Table 5 14 PLD Boot Bank Register REG PLD Boot Bank 0xFFDF0050 Bit 7 6 5 4 3 2 1 0 Field SPI_GOODReg write 0xA4 into this reg to indicate successful loading of the U Boot BOOT_B LOCK_A BOOT_S PI OPER R W R R R...

Page 107: ...FLASH_ WP_N I2C_DEB UG_EN SERIAL_ FLASH_ WP RSVD I2C_1_D I2C_1_C OPER R R R R W R W R R W R W RESET 0 1 0 0 1 0 1 1 Field Description SPD_WP SPD write protection 0 SPD Writes enabled 1 SPD Writes disabled MASTER_WP MASTER WP Switch S2 6 0 Switch S2 6 closed SPI SPD VPD USER FLASH write enable 1 Switch S2 6 open register bits control write protectioN USER_WP USER FLASH write protect 1 USER I2C FLAS...

Page 108: ...gister which is used by the software for PLD testing or general status bit storage When SERIAL_FLASH_WP is set to LOW this port will automatically read as low due to AND connection between the two ports Table 5 16 PLD Test Register 1 REG PLD Write Protect I2C Debug 0xFFDF0095 Bit 7 6 5 4 3 2 1 0 Field TEST_REG1 OPER R W RESET 00 Field Description TEST_REG1 General purpose 8 bit R W field ...

Page 109: ...evice the interrupt originated from GPIO2 will be driven low if any of the interrupts asserts Table 5 17 PLD Test Register 2 REG PLD Write Protect I2C Debug 0xFFDF0095 Bit 7 6 5 4 3 2 1 0 Field TEST_REG1 OPER R W RESET 00 Field Description TEST_REG2 General purpose 8 bit R W field Table 5 18 PLD GPIO2 Interrupt Register REG PLD Write Protect I2C Debug 0xFFDF0095 Bit 7 6 5 4 3 2 1 0 Field CPU_RT C_...

Page 110: ...NT Tick Timer 1 interrupt 1 Interrupt enabled 0 No Interrupt TICK2_INT Tick Timer 2 interrupt 1 Interrupt enabled 0 No Interrupt Table 5 19 PLD Shutdown and Reset Control and Reset Reason Register REG PLD Shutdown and Reset Reason 0xFFDF00FF Bit 7 6 5 4 3 2 1 0 Field RSVD Shutdown Soft_ RST Clear_ Cause CPU_ RESET WD_TIME OUT LRSTO Sft_RST OPER R W W W R RESET 0 0 0 0 X X X X Field Description Shu...

Page 111: ...t is due to watchdog timing out 0 None LRSTO TSI LRSTO Reset Reason 1 Reset is due to LRSTO signal 0 None Sft_RST Soft Reset Reset Reason 1 Reset is due to Soft_RST register being set or the front panel switch being pressed more than three 0 None Table 5 20 PLD Shutdown and Reset Control and Reset Reason Register REG EMMC Reset Register Bit 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD ...

Page 112: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Refresh OPER R RESET 0000 Field Description Refresh Counter Refresh When the pattern 0x00DB is written the watchdog counter will be reset to zero Table 5 22 PLD Watchdog Control Register REG PLD Watch Dog Timer Load 0xFFC80604 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Watchdog _EN RSV D RSV D RSV D RSV D RSV D RSV D...

Page 113: ...ield Description Count Count These bits define the watchdog timer count value When the watchdog counter is enabled it will count up from zero reset value with a 1 ms resolution until it reaches the COUNT value set by this register Watchdog will generate a soft reset signal if it bites Setting this register to 0xEA60 or 60 000 counts will provide a watchdog timeout of 60 seconds Table 5 24 PLD Watc...

Page 114: ...ust value is determined by this formula Prescaler Adjust 256 CLKIN CLKOUT CLKIN is the input clock source in MHz and CLKOUT is the desired output clock reference in MHz The prescaler provides the clock required by each of the three times The tick timers require a 1MHz clock input The input clock to the prescaler is 25MHz The default value is set for 0x00E7 which gives 1MHz reference clock for 25MH...

Page 115: ...7 6 5 4 3 2 1 0 Field RSVD INTS CINT ENINT OVF RSVD COVF COC ENC OPER R W RESET 0x0000 Field Description ENC Enable counter When the bit is set the counter increments When the bit is cleared the counter does not increment COC Clear Counter on Compare When the bit is set the counter is reset to 0 when it compares with the compare register When the bit is cleared the counter is not reset COVF Clear ...

Page 116: ...gister was split in half Accessing the whole register will require two transactions Table 5 27 Compare High Word Registers REG Tick Timer 0 Compare Value High Word 0xFFC80204 Tick Timer 1 Compare Value High Word 0xFFC80304 Tick Timer 2 Compare Value High Word 0xFFC80404 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field TickTimer Compare Value High Word 16 bits OPER R W RESET 0x0000 Table 5 28 Compar...

Page 117: ...ord 0xFFC80208 Tick Timer 1 Counter Value High Word 0xFFC80308 Tick Timer 2 Counter Value High Word 0xFFC80408 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field TickTimer Counter Value High Word 16 bits OPER R W RESET 0x0000 Table 5 30 Counter Low Word Registers REG Tick Timer 0 Counter Value Low Word 0xFFC8020A Tick Timer 1 Counter Value Low Word 0xFFC8030A Tick Timer 2 Counter Value Low Word 0xFFC...

Page 118: ...118 MVME2502 Installation and Use 6806800R96L Memory Maps and Registers Memory Maps and Registers ...

Page 119: ... software based on the GNU Public License It boots the blade and is the first software to be executed after the system is powered on Its main functions are Initialize the hardware Pass boot parameters to the Linux kernel Start the Linux kernel Update Linux kernel and U Boot images The below sections describe U Boot features and procedures that are specific to the MVME2502 For general information o...

Page 120: ...dress of MVME2502 setenv serverip IP address of TFTP server setenv gatewayip gateway IP setenv netmask netmask setenv bootargs root dev ram rw console ttyS0 9600n8 ramdisk_size 700000 cache sram size 0x10000 saveenv 3 Transfer the files through the TFTP from the server to the local memory tftp 1000000 kernel_image tftp 2000000 ramdisk tftp C00000 kernel dtb 4 Boot the Linux from the memory bootm 1...

Page 121: ...d scsi 0 1 2000000 File_ramdisk ext2load scsi 0 1 c00000 File_dtb 4 Boot the Linux in memory bootm 1000000 2000000 c00000 6 3 3 Booting from a USB Drive 1 Make sure that the kernel dtb and ramdisk are saved in the USB drive with FAT partition 2 Configure the U Boot environment variable setenv File_uImage kernel_image setenv File_dtb kernel dtb setenv File_ramdisk ramdisk saveenv 3 Initialize USB d...

Page 122: ...t the Linux in memory bootm 1000000 2000000 c00000 6 3 5 Booting VxWorks Through the Network In this mode the U Boot downloads and boots VxWorks from an external TFTP server 1 Make sure that the VxWorks image is accessible to the board from the TFTP server 2 Configure U Boot environment variables setenv ipaddr IP address of MVME2502 setenv serverip IP address of TFTP server setenv gatewayip gatewa...

Page 123: ...he faceplate button to analyze the cause then subsequently analyze kernel log files The persistent memory feature keeps the log files available in the memory To analyze the kernel log files 1 Issue a reset 2 Connect to U Boot For more information see Accessing U Boot on page 119 3 Enter the following command to obtain memory addresses of the kernel log files locate_kernel_log 1 The memory addresse...

Page 124: ...m memory bootp Boot image through network using BOOTP TFTP protocol bootvx Boot VxWorks from an ELF image cmp Memory compare coninfo Print console devices and information cp Memory copy cpu Multiprocessor CPU boot manipulation and release crc32 Checksum calculation date Get set reset date time diags Runs POST diags echo Echo args to console exit Exit script ext2load Load binary file from a Ext2 fi...

Page 125: ...ver serial line kermit mode loads Load S Record file over serial line loady Load binary file over serial line ymodem mode loop Infinite loop on address range md Memory display memmap Displays memory map mii MII utility commands mm Memory modify auto incrementing address mmc MMC sub system mmcinfo Display MMC info moninit Reset nvram serial and write monitor to SPI flash mtest Simple RAM read write...

Page 126: ...ipt Run a delimited terminated list of commands scsi SCSI sub system scsiboot Boot from SCSI device setenv Set environment variables setexpr Set environment variable as the result of eval expression sf SPI flash sub system showvar Print local hushshell variables sleep Delay execution for some time soft_reset Soft reset the board source Run script from memory test Minimal test like bin sh tftpboot ...

Page 127: ... Disable SPI write protect in CPLD register PLD Write Protect and I2 C Debug Register on page 107 2 Ensure FLASH_WP_N in SMT configuration switch S2 is in the OFF position 3 Select SPI flash 0 sf probe 0 4 Erase 0x90000 bytes starting at SPI address 0 sf erase 0 0x90000 5 Write 0x90000 bytes from RAM address 0x1000000 starting at SPI address 0 sf write 0x1000000 0 0x90000 To replace the image in S...

Page 128: ...128 MVME2502 Installation and Use 6806800R96L Boot System Boot System ...

Page 129: ...88_CLK_ OUT TSEC_1588_PULSE _OUT1 TSEC_1588_PULSE _OUT2 001 8 1 DDR PLL 800MHz DDR rate is twice the value of the DDR controller frequency which is then divided by two through the software 3 Core 0 PLL LBCTL LALE LGPL2 LOE LFRE 110 3 1 CORE CLOCK PLL 1200MHz For 1200MHz board configuration 100 2 1 CORE CLOCK PLL 800MHz For 800MHz board configuration 4 Core 1 PLL LWE0 UART_SOUT1 110 3 1 CORE CLOCK ...

Page 130: ...C Enable Config MSRCID0 0 Default operation eLBC ECC checking is disabled 10 Platform Speed LA23 1 CFG_PLAT_SPEED 1 CCB CLOCK 333 MHz 11 CORE 0 Speed LA24 1 CFG_CORE0_SPEED 1 CORE FREQ 1000 MHz For 1200MHz board configuration 12 0 CFG_CORE0_SPEED 0 CORE FREQ 1000 MHz For 800MHz board configuration 13 CORE 1 Speed LA26 1 CFG_CORE1_SPEED 1 CORE FREQ 1000 MHz For 1200MHz board configuration 14 0 CFG_...

Page 131: ...es the TSEC_2 pins default 19 ETSEC3 SGMMI Mode TSEC_1588_ALAR M_OUT2 1 eTSEC3 Ethernet interface operates in standard parallel interface mode and uses the TSEC_3 pins default 20 ETSEC1 and ETSEC2 Width EC_MDC 0 eTSEC1 and eTSEC2 Ethernet interfaces operate in reduced pin mode either RTBI RGMI RMII or 8 bit FIFO mode 21 ETSEC1 Protocol TSEC1_TXD0 TSEC1_TXD7 10 The eTSEC2 controller operates using ...

Page 132: ...011X On chip boot ROM SPI configuration x 0 SDHC x 1 25 Host Agent Config LWE1 LBS1 LA 18 19 111 The processor acts as the host root complex for all PCI E Serial Rapid IO interfaces default 26 I O Port Select TSEC1_TXD 3 1 TSEC2_TX_ER 0010 PCI E 1 x1 2 5 Gbps SerDes lane 0 PCI E 2 x1 2 5 Gbps SerDes lane 2 PCI E 3 x2 2 5 Gbps SerDes lane 2 3 27 DDR SDRAM TYPE TSEC2_TXD1 1 DDR31 5 V CKE low at rese...

Page 133: ...nfiguration Settings continued CONFIG CONFIG PINS CONFIG SELECTION REMARKS Table 7 2 MVME2502 Interrupt List Interrupt Line Interrupt Usage Schematic Interface to CPU Description IRQ0 None Reserved for VME interrupt IRQ1 QUART_IRQ1 LBC RTB Quart Interrupt IRQ2 QUART_IRQ2 LBC RTB Quart Interrupt IRQ3 QUART_IRQ3 LBC RTB Quart Interrupt IRQ4 Temperature Interrupt I2C Two on board Thermal Sensors one ...

Page 134: ...XMC EEPROM is configured through Geographic Address resistor on board IRQ8 GPIO1 RTC Real Time Clock 12C DS1337 INT_A IRQ9 GPIO2 CPLD Interrupt LBC NMI and 3 Tick Timer Interrupts IRQ10 GPIO3 CPLD Interrupt LBC Not used IRQ11 GPIO4 QUART_IRQ0 LBC RTB Quart Interrupt Table 7 2 MVME2502 Interrupt List continued Interrupt Line Interrupt Usage Schematic Interface to CPU Description Table 7 3 I2 C Bus ...

Page 135: ...DS1375 Real Time Clock RTC chip The RTC chip provides time keeping and alarm interrupts It is an I2 C device and is accessed through the I2 C bus address at 0x68 7 6 3 Quad UART The MVME2502 console RS 232 port is driven by the UART built into the P2020 QorIQ chip Additionally the MVME2502 has a Quad UART chip which provides four 16550 compatible UARTs These additional UARTs are internally accesse...

Page 136: ...escription BCTLD Buffer control disable 0 LBCTL is asserted upon access to the current memory bank CSNT Chip Select negation time 1 LCSn and LWE are negated one quarter of the bus clock cycle earlier ACS Address to chip select setup 10 LCSn is outputted one quarter bus clock cycle after the address lines XACS Extra Address to chip select setup 0 Address to chip select setup is determined by ORx AC...

Page 137: ...erates normal timing No additional cycles are inserted EAD External address latch delay 0 No additional bus clock cycles LALE asserted for one bus clock cycle only Table 7 6 Clock Distribution Device Clock Signal Frequency Clock Tree Source VIO QorIQ P2020 CPU_SYSCLK 100MHz ICS840S07I 3 3V QorIQ P2020 CPU_DDR_CLK 100MHz ICS840S07I 3 3V QorIQ P2020 CLK_PCI_BR3 133MHz ICS840S07I 3 3V QorIQ P2020 EC_...

Page 138: ...C3 100MHz ICS9FG111 DIFF 88SE9125 CLK_88SE9125_PCIE_100 MHZ 100MHz ICS9FG112 DIFF CPLD CLK_CPLD 1 8432MHz Oscillator 3 3V USB CLK_USB_1_24MHZ 24MHz Oscillator 3 3V QorIQ P2020 CPU_RTC 1MHz CPLD 3 3V PMC CLK_PMC1 33 66 100 133 MHz TSI384 3 3V TSI148 CLK_PCI_BR3 133MHz ICS840S07I 3 3V RTC CLK_32K 32 768KHz DS32KHz 3 3V CPLD CPU_LCK0 25MHz QorIQ P2020 3 3V QUART CLK_QUART 1 8432MHz CPLD 3 3V ICS83905...

Page 139: ...Installation and Use 6806800R96L 139 7 7 3 Local Bus Controller Clock Divisor The local bus controller LBC clock output is connected to the CPLD for LBC bus transaction It is also the source of 1 MHz CPU_RTC and CPLD tick timers ...

Page 140: ...140 MVME2502 Installation and Use 6806800R96L Programming Model Programming Model ...

Page 141: ...MVME2502 Installation and Use 6806800R96L 141 Appendix A Replacing the Battery A 1 Replacing the Battery The figure below shows the location of the board battery Figure A 1 Battery Location ENP1 Variant ...

Page 142: ...142 MVME2502 Installation and Use 6806800R96L Replacing the Battery Replacing the Battery Figure A 2 Battery Location ENP2 Variant ...

Page 143: ...s can result in a hazardous explosion When replacing the on board lithium battery make sure that the new and the old battery are exactly the same battery models If the respective battery model is not available contact your local Penguin Solutions sales representative for the availability of alternative officially approved battery models Data Loss Replacing the battery can result in loss of time se...

Page 144: ...144 MVME2502 Installation and Use 6806800R96L Replacing the Battery Replacing the Battery ...

Page 145: ...itional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table B 1 Penguin Edge Documentation Document Title Document Number MVME2502 Data Sheet MVME2502 DS MVME2502 Quick Start Guide 6806800S32 MVME2502 Safety Notes 6806800S33 MVME721X RTM Installation and Use 6806800M42 MVME721X RTM Quick...

Page 146: ...rocessor PMC VITA Standards Organization XMC High Speed Switched Interconnect Protocols on PMC VITA 42 0 2005 XMC General Purpose I O Standard VITA 42 10 XMC PCI Express Protocol Layer Standard VITA 42 3 2006 IEEE IEEE 802 3 LAN MAN CSMA CD Access Method IEEE 802 3 2005 IEEE Standard for a Common Mezzanine Card CMC Family IEEE Std 1386 2001 IEEE Standard Physical and Environmental Layers for PCI M...

Page 147: ... ATA SATA Specification Revision 2 6 Serial ATA II Extensions to Serial ATA 1 0 Revision 1 0 Trusted Computing Group TCG TPM Specification 1 2 Level 2 Revision 103 Version 1 2 USB Implementers Forum USB IF Universal Serial Bus Specification USB Revision 2 0 Table B 3 Related Specifications continued Organization Document ...

Page 148: ...148 MVME2502 Installation and Use 6806800R96L Related Documentation Related Documentation ...

Page 149: ...1 ...

Page 150: ... SMART Global Holdings Inc Penguin Edge is a trademark owned by Penguin Computing Inc a wholly owned subsidiary of SMART Global Holdings Inc NXP and QorIQ are trademarks of NXP B V All other logos trade names and trademarks are the property of their respective owners 2022 SMART Embedded Computing Inc ...

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