SMART Embedded Computing MVME2502, Installation And User Manual

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74 MVME2502 Installation and Use (6806800R96L)
Functional Description
Functional Description
4.2 Chipset
The MVME2502 utilizes the QorIQ P20x0 integrated processor. It offers an excellent
combination of protocol and interface support which includes the following components.

QorIQ P2020 integrated processor or e500 processor core

PCI Express interface

Local Bus Controller

Secure Digital Host Controller

I2C interface

USB interface

DUART

DMA controller

Enhanced three speed Ethernet controller

General Purpose I/O (GPIO)

Integrated Security Engine

Common On-chip Processor

P2020 Strapping pins
4.2.1 e500 Processor Core
The e500v2 (P2020) QorIQ integrated processor offers high performance dual core. It
operates from 1.0GHz up to 1.2GHz core frequency. The e500 processor core is a low-
power implementation of the family of reduced instruction set computing (RISC) embedded
processor that implement the Book E definition of the PowerPC architecture. The e500 is
a 32-bit implementation of the Book E architecture using the lower words of 64-bit general-
purpose registers (GPRs) while E500v2 uses 36 bit physical addressing.
4.2.2 Integrated Memory Controller
A fully programmable DDR SDRAM controller supports most JEDEC standard DDR2 and
DDR3 memories available. A built-in error checking and correction (ECC) ensures very low
bit-error rates for reliable high-frequency operation. ECC is implemented on MVME2502.
The memory controller supports the following:

16GB of memory

Asynchronous clocking from platform clock, with programmable settings that
meets all the SDRAM timing parameters.