ATCA-F140 Series Installation and Use (6806800M67S)
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Chapter 4
Functional Description
4.1
Block Diagram
The following block diagram provides a high level functional view of the ATCA-F140 blade
and its interfaces to the front panel, backplane, and RTM.
4.2
Processor
The ATCA-F140 utilizes an NXP QorIQ P2020 processor. The speed grade used on the
ATCA-F140 is 1.0GHz.
The QorIQ P2020 Integrated Processor provides the following features:
Dual e500 cores
On-die 32KB L1 cache for each core
On-die common 512KB L2 cache with ECC
DDR3 memory controller and interface
Figure 4-1 ATCA-F140 Block Diagram
RTM-ATCA-F140
SFI
SFI
SFI
SFI
FC 1
To Other
Hub
Board
12x 40G-KR4
40
40 40 40 40
40 40 40 40 40 40 40
Backplane Zone 2
Connectors
Logical Slot
3
4
5
6
7
8
9
10 11
12 13 14 15 16
1 = 1G-KX/BX
40 = 40G-KR4, 4x 10G-KR,
10G-KX4/BX4, 1G-KX/BX
XLAUI / 4x XFI
QSFP+
ETH1
To Zone 3
Broadcom
BCM56334
24x 1G-KX +
4x 10G-XAUI
SATA
Ports 8-11
Port 2
To Zone 3
x2 PCIe
x1 PCIe
NXP
P2020
Processor
RGMII
RS232
54616S
PHY
1G-T
xcvr
UART
Ports 4-7
RJ45
ETH5
RJ45
CONSOLE
12x 1G-SGMII
Transformers
54680
PHYs
10G-XAUI
BCM8727
2x
XAUI<>SFI
SFI
Port 0
Port 1
2x 10G-XAUI
To Zone 3
Boot+Kernel
NOR Flash
Local Bus
Boot+Kernel
NOR Flash
x1 PCIe
UC[2]
SATA
HDD
Backplane
USB
PHY
FileSystem
NAND Flash
1G-
SERDES
2x 1G-SGMII
Broadcom
BCM56846
64x 10G-KR
+ 4x 1G-KX
2x1G-SGMII
82571EB
2x1GbE
MAC/PHY
PCI-E x4
1G-SGMII
1G-SGMII
UC[3:4]
Fabric X-Connect:
Tx to UC[4]; Rx to UC[3]
Fabric X-Connect:
Tx to UC[3]; Rx to UC[4]
AMC=>Fabric
X-Connect
Fabric=>AMC
X-Connect
UC[0:1]
Base X-Connect:
Tx to UC[1]; Rx to UC[0]
Base X-Connect:
Tx to UC[0]; Rx to UC[1]
AMC=>Base
X-Connect
Base=>AMC
X-Connect
1G-SGMII
1G-SGMII
1
1
SATA
Bridge
RGMII
54616S
PHY
PPI
IPMC
Host
Interface
IPMB-0
Bussed
to
ShMCs/
Blades
To Service
Processor
TCLK
1/2/3
CLK[1:3][A:B]
Bussed
to
Blade
Slots
Clock FPGA
Semtech
TopSync
MLVDS
Stratum 3
Oscillator
Maxim
26503
Framers
Trans
formers
Maxim
26503
Framers
Trans
formers
2x
RJ-45
6x
RJ-45
MLVDS
SPI to Processor
5241
PHY
54616S
PHY
10/100-MII
BC 1[A]
BC 1[B]
1G-SGMII
1G-SGMII
BC 2
To
ShMCs
10/100-T
10/100-T
1G-T
54680
PHY
Trans
formers
54616S
PHY
Trans
former
1G-SGMII
4x 1G-SGMII
To Zone 3
1G-SGMII
1G-SGMII
To Zone 3
1G-SGMII
2x 10G-XAUI
BCM84754
4x XFI <>
SFI
BCM84740
XLAUI <>
PPI
SFP+
ETH6
SFP+
ETH5
SFP+
ETH4
SFP+
ETH3
QSFP+
ETH7
SFI
SFP+
ETH1
SFI
SFP+
ETH2
BCM8727
2x XAUI <>
SFI
1 1 1 1 1 1 1 1 1 1 1 1
Backplane Zone 2
Connectors
14x 1G-T
Logical Slot
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1 1
2x 1G-SGMII
To Zone 3
4x 1G-SGMII
FPGA
QSFP+
ETH2
BCM84740
XLAUI<>PPI
PPI / 4x SFI
PPI / 4x SFI
SFP+
ETH3
SFP+
ETH4
2x BITS/SSU
5x Inter-Shelf Sync
Master/Slave Sync
Front
Panel
SFP
ETH8
SFP
ETH9
SFP
ETH10
SFP
ETH11
To Zone 3
1G-SGMII
AMC
1G-
SERDES
DIMM1
DDR3
w/ ECC
DIMM2
DDR3
w/ ECC
Hot
Swap
Control
P17
P18
HG0-HG1
P19
P20-
P23
HG2
P0-
P11
P12-P13
P16
P14
P15
PCIe
WC0
lane 3
PCIe
WC0
lane 2
WC0
lanes 0-1
WC1-
WC12
XLAUI / 4x XFI
WC16
WC17
SFI
4x XFI
XLAUI / 4x XFI
WC15
WC14
To Zone 3
4x XFI
XLAUI /
4x XFI
ATCA-F140
BCM84740
XLAUI<>PPI
TopSync Fabric
TopSync Fabric
10G-XAUI
HG3
4x SFI
Shaded area indicates circuitry
for the Telecom Clock feature
Clock Distribution
25MHz
100MHz PCIE
156.25MHz
100MHz
125MHz
