Functional Description
ATCA-F140 Series Installation and Use (6806800M67S)
109
The request output signal HRESET_REQ_L of the QorIQ P2020 Integrated Processor
indicates to the blade that a condition requiring the assertion of HRST_L has been
detected. HRESET_REQ_L may be activated by a watchdog timer inside the QorIQ P2020
Integrated Processor, a boot sequence failure or by software. HRESET_REQ_L may occur
at any time synchronous to the core complex bus clock and stays active until HRST_L is
asserted.
The soft reset input signal SRST_L causes a machine check interrupt to both e500 cores
of the QorIQ P2020 Integrated Processor. SRST_L need not to be asserted during a hard
reset. SRST_L may be asserted at any time completely asynchronously.
An output signal READY from each core indicates to the blade that the cores have
completed the reset operation and are not in a power-down state. This information is
monitored by the IPMC.
4.11.1.2 Memory
The registers of the registered DIMM(s) will be reset in parallel to the HRST_L signal of the
QorIQ P2020 Integrated Processor.
4.11.1.3 On-board Flash
All on-board boot flash devices which are attached to the local bus are reset in parallel
when the HRST_L signal is asserted.
4.11.1.4 Persistent Memory
The persistent memory is only reset after power-on reset. In all other on-board reset events,
the persistent memory is not reset if the persistent memory feature has been enabled.
4.11.2
Ethernet Switch Resets
4.11.2.1 Broadcom BCM56334
A power-on or hard reset is initiated by an active low pulse on the RESET_L signal of the
Broadcom BCM56334 Base Channel Switch. The initialization process loads all the pin
configurable modes, clears all switching tables and places the switch in a disabled and idle
state.
4.11.2.2 Broadcom BCM56846
A power-on or hard reset is initiated by an active low pulse on the SYS_RST_L signal of
the Broadcom BCM56846 Fabric Channel Switch. The initialization process loads all the
pin configurable modes, clears all switching tables and places the switch in a disabled and
idle state.
