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8.7 Output Delay Control

The input to output skew can be adjusted dynamically. This involves changing the output phase of the N divider; so the phase for all
outputs that are driven by a given Nx will change together.The dynamic phase adjust can be initiated at any time under register control.
This adjustment can change the output phase by up to 360 degrees (i.e. one UI). The resolution values listed in the table below assume
a VCO frequency of 14 GHz for a Tvco of 71.43 psec. The skew value may change after each reset or power cycle.

Table 8.16. Input-Output Skew Control Registers

Type

Setting Names

Setting Address Start

Typical Resolution

Dynamic

Nx_PHASE_STEP,

Nx_PHASE_COUNT

0x0A38

T

VCO

= 71.43 ps

For more details on how these registers are enabled and programmed, see the appropriate register map section toward the end of this
reference manual.

Si5391 Reference Manual • Outputs

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com

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Rev. 0.5 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 11, 2022

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Summary of Contents for Si5391

Page 1: ...rogrammable via a serial interface with in circuit programma ble nonvolatile memory NVM ensuring power up with a known frequency configura tion RELATED DOCUMENTS Si5391 Data Sheet Si5391 Device Errata Si5391 EVB User Guide Si5391 EVB Schematics BOM Layout IBIS models Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 1 Rev 0 5 Skyworks Proprietary ...

Page 2: ...al on XA XB 17 7 2 2 Clock Input on XA XB 18 7 2 3 Clock Inputs on IN2 IN1 IN0 19 7 2 4 Unused Inputs 20 7 2 5 Input Clock Rise Time Considerations 20 7 3 Fault Monitoring 21 7 3 1 Status Indicators 22 7 3 2 Interrupt Pin INTR 23 8 Outputs 25 8 1 Output Crosspoint Switch 25 8 2 Output Divider R Synchronization 26 8 3 Performance Guidelines for Outputs 27 8 4 Output Signal Format 28 8 4 1 Different...

Page 3: ... Si5391 Si5391P Layout Recommendations 51 12 1 1 Si5391 with an External Reference Not Relevant to the Si5391P 51 12 1 2 Si5391 Si5391P Crystal Guidelines 52 12 1 3 Si5391 Si5391P Output Clocks 58 13 Power Management 60 13 1 Power Management Features 60 13 2 Power Supply Recommendations 60 13 3 Power Supply Sequencing 61 13 4 Grounding Vias 61 14 Register Map 62 14 1 Base vs Factory Preprogrammed ...

Page 4: ...n History 93 Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 4 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice January 11 2022 4 ...

Page 5: ...d configure for the end application The software walks the user through each step with explanations about each configuration step in the process to explain the different options available The software will restrict the user from entering an invalid combination of selections The final configuration settings can be saved written to an EVB and a custom part number can be created for customers who pre...

Page 6: ... CBPro with visual feedback so that it is simple to develop a plan that guarantees 100 fs jitter on the 156 25 312 5 625 MHz output clocks A 156 25 312 5 625 MHz output will be labeled by CBPro as Precision when it will achieve less than 100 fs jitter 2 2 1 Output Clock Domains The Si5391P is only allowed to output a fixed set of frequencies These frequencies are grouped into 3 clock domains Domai...

Page 7: ... or 3 clock that is adjacent to 156 25 312 5 625 MHz may couple too much energy to allow these Domain 1 clocks to meet 100 fs clocks Therefore domain 2 and 3 clocks must be isolated from 156 25 312 5 625 MHz outputs In addition to the tables above ClockBuilder Pro enforces gaps between domain 1 and domain 2 outputs ClockBuilder Pro makes it simple to achieve 156 25 312 5 625 MHz outputs that are g...

Page 8: ... and the output integer dividers R Skyworks Clockbuilder Pro configuration utility determines the optimum divider values for any desired input and output frequency plan The output drivers offer flexible output formats which are independently configurable on each of the outputs This clock generator is fully configurable via its serial interface I2C SPI and includes in circuit programmable non volat...

Page 9: ... newly written divider value to take effect 4 Output N dividers Ultra low jitter in fractional and integer modes MultiSynth divider Integer or fractional divide values 44 bit numerator 32 bit denominator Min value is 10 Maximum value is 212 1 Each N divider has an update bit that must be written to cause a newly written divider value to take effect In addition there is a global update bit that whe...

Page 10: ...y re starts the internal initialization sequence NVM 2x OTP RAM NVM Download Figure 4 2 Si5391 Si5391P Memory Configuration Table 4 1 Reset Control Registers Register Name Hex Address Bit Field Function Si5391 HARD_RST 001E 1 Performs the same function as power cycling the device All registers will be restored to their default values SOFT_RST 001C 0 Performs a soft reset Resets the device while it...

Page 11: ...d values will match Please contact Skyworks if you need information about an earlier revision Please always ensure to use the correct sequence for the correct revision of the device Also check for the latest information online This information is updated from time to time The latest information is always posted online 5 1 Dynamic Changes to Output Frequencies without Changing PLL Settings This sec...

Page 12: ... a Si5391 2 This needs a register write sequence provided in the CBPro export section as shown below Figure 5 1 CBPro Register Write Sequence While Changing PLL Settings Si5391 Reference Manual Dynamic PLL Changes Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 12 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subj...

Page 13: ...Write 0xC7 to NVM_WRITE register This starts the internal NVM burn sequence writing NVM from the internal registers Do not access ANY other registers than DEVICE_READY during the NVM burn process Doing so may corrupt the NVM burn in progress 4 Poll DEVICE_READY until DEVICE_READY 0x0F waiting for completion of NVM burn sequence 5 Set NVM_READ_BANK 0x00E4 0 1 This will download the NVM contents bac...

Page 14: ...eads as 0x0F may corrupt the NVM programming and may corrupt the register contents as they are read from NVM Note that this includes accesses to the PAGE register Si5391 Reference Manual NVM Programming Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 14 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Chan...

Page 15: ...OUT2 OUT3b VDDO3 OUT3 OUT4b VDDO4 OUT4 OUT5b VDDO5 OUT5 OUT6b VDDO6 OUT6 OUT7b VDDO7 OUT7 OUT 8b VDDO8 OUT8 OUT9b VDDO9 OUT9 OUT1b VDDO1 OUT1 Pfb LPF PD Mn Md PLL IN_SEL 1 0 XA XB P2 P1 P0 IN0 IN0b IN1 IN1b IN2 IN2b FDEC FINC Frequency Control N0n N0d t0 N2n N2d N3n N3d N4n N4d t2 t3 t4 N1n N1d t1 MultiSynth SYNCb Dividers Drivers Status Monitors LO Lb INTRb OSC PXAXB 25 54 MHz XTAL R9A OUT9Ab OUT...

Page 16: ...s 0 XTAL Set to 1 to use an external ref erence oscillator It must always be set to 0 default for Si5391P IN_SEL_REGCTRL 0021 0 Determines pin or register clock input selection IN_SEL 0021 2 1 Selects the input when in register input selection mode IN_EN 0949 3 0 Allows enabling disabling IN0 IN1 IN2 and FB_IN when not in use Table 7 3 XAXB Pre Scale Divide Ratio Register Setting Name Hex Address ...

Page 17: ...stals with CL specs higher than 8 pf it is not generally recommended to use external capacitors from XA XB to ground to increase the crystal load capacitance See Section 12 Crystal XO and Device Circuit Layout Recommendations for the PCB layout guidelines For Si5391P devices the crystal frequency MUST be 48 MHz and have a loading capacitance of 8 pf No external loading capacitors are needed since ...

Page 18: ... Figure 7 2 Crystal Resonator and External Reference Clock Connection Options In addition to crystal operations the Si5391 accepts a clipped sine wave CMOS or differential reference clock on the XA XB interface Most clipped sine wave and CMOS TCXOs have insufficient drive strength to drive a 100 Ω or 50 Ω load For this reason place the TCXO as close to the Si5391 as possible to minimize PCB trace ...

Page 19: ...s connected to ground with a 4 7 kΩ or smaller resistor then the INx can be powered up or down when it does not have an input The recommended input termination schemes are shown in the figure below Unused inputs can be disabled by register configuration 50 100 INx INxb 50 Standard AC Coupled Differential LVDS LVPECL CML Standard AC Coupled Single Ended INx 3 3V 2 5V 1 8V LVCMOS R1 R2 50 RS RS matc...

Page 20: ...ut jitter will increase The following figure shows the effect of a low slew rate on RMS jitter for a differential clock input It shows the relative increase in the amount of RMS jitter due to slow rise time and is not intended to show absolute jitter values 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 0 100 200 300 400 500 600 Relateive Jitter Input Slew V us IN_X Slew Rate in Differential Mode JTYP Figure 7 4...

Page 21: ...e and configuration of status fault monitoring features as well as mapping these to the INTRb output are described on following sub sections PLL LPF PD Mn IN0 IN0b LOS0 P0 IN1 IN1b P 1 FB_IN FB _INb IN2 IN2b P2 LOL Si5391 XB XA OSC Pfb Md LOSXAB LOS1 LOS2 LOLb INTRb LOSFB Figure 7 5 Fault Monitors Si5391 Reference Manual Clock Inputs Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales...

Page 22: ...t have an LOS detector LOSREF 0x000C 2 Loss of Signal for the input that has been selected LOL 0x000C 3 Loss of Lock for the PLL SMBUS_TIMEOUT 0x000C 5 The SMB bus has a timeout LOSIN 3 0 0x000D 3 0 Loss of Signal for the FB_IN IN2 IN1 IN0 inputs Sticky Status Register Bits SYSINCAL_FLG 0x0011 0 Sticky bit for SYSINCAL LOSXAXB_FLG 0x0011 1 Sticky bit for LOSXAXBB LOSREF_FLG 0x0011 2 Sticky bit for...

Page 23: ...OSREF_INTR_MSK 0x0017 2 1 LOSREF_FLG is prevented from asserting the INTR pin LOL_INTR_MSK 0x0017 3 1 LOL_FLG is prevented from asserting the INTR pin SMB_TMOUT_INTR_MSK 0x0017 5 1 SMBUS_TIMEOUT_FLG is prevented from asserting the INTR pin LOSIN _INTR_MSK 3 0 0x0018 3 0 1 LOS_FLG is prevented from asserting the INTR pin mask mask mask mask mask mask LOL_FLG LOSXAXB_FLG LOSIN_FLG 3 LOSIN_FLG 2 LOSI...

Page 24: ... _FLG bit will cause an interrupt For example if LOS_FLG 0 is high and LOS_INTR_MSK 0 is low then the INTR pin will be active low and cause an interrupt If LOS 0 is zero and LOS_MSK 0 is one writing a zero to LOS_MSK 0 will clear the interrupt assuming that there are no other interrupt sources If LOS 0 is high then LOS_FLG 0 and the interrupt cannot be cleared Note The INTR pin may toggle during r...

Page 25: ...R0 R2 R3 R4 R5 R6 R7 R8 R9 R1 OUT0b VDDO0 OUT0 OUT2b VDDO2 OUT2 OUT3b VDDO3 OUT3 OUT4b VDDO4 OUT4 OUT5b VDDO5 OUT5 OUT6b VDDO6 OUT6 OUT7b VDDO7 OUT7 OUT 8b VDDO8 OUT8 OUT9b VDDO9 OUT9 OUT1b VDDO1 OUT1 Pfb LPF PD Mn Md PLL IN_SEL 1 0 XA XB P2 P1 P0 IN0 IN0b IN1 IN1b IN2 IN2b FDEC FINC Frequency Control N0n N0d t0 N2n N2d N3n N3d N4n N4d t2 t3 t4 N1n N1d t1 MultiSynth SYNCb Dividers Drivers Status M...

Page 26: ...set This ensures consistent and repeatable phase alignment across all output drivers coming from the same N divider Resetting the device using the RSTb pin or asserting the hard reset bit will have the same result The SYNCb pin provides another method of realigning the R dividers without resetting the device This pin is positive edge triggered Asserting the sync register bit provides the same func...

Page 27: ...lowed and these outputs should be grouped together when possible Noting that because 155 52 MHz x 4 622 08 MHz it is okay to place the pair of these frequency values close to one another 3 Unused outputs can be used to separate clock outputs that might otherwise interfere with one another If some outputs have tight jitter requirements while others are relatively loose rearrange the clock outputs s...

Page 28: ...ngle ended outputs Note also that CMOS output can create much more crosstalk than differential outputs so extra care must be taken in their pin replacement so that other clocks that need the lowest jitter are not on nearby pins See AN862 Optimizing Jitter Performance in Next Generation Internet Infrastructure Systems for additional information Table 8 3 Output Signal Format Control Registers Setti...

Page 29: ... 50 50 Internally self biased OUTx OUTxb LVDS VDDO 3 3V 2 5V 1 8V LVPECL VDDO 3 3V 2 5V VDDRX R1 R2 3 3 V 2 5 V 1 8 V 442 332 243 56 2 59 0 63 4 For VCM 0 35 V All caps should have 5 ohms capacitive reactance at the clock output frequency 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF Figure 8 2 Supported Differential Output Terminations Si5391 Reference Manual Outputs Skyworks Solutions Inc Phone 781 376 30...

Page 30: ...impedance mode and supports standard 50 Ω PCB traces Any of the terminations shown in Figure 8 2 Supported Differential Output Terminations on page 29 are supported The use of High Swing mode will result in larger pk pk output swings that draw less power The trade off will be slower rise and fall times Vpp_diff is 2 x Vpp_se as shown below OUTx OUTx Vpp_se Vpp_se Vpp_diff 2 Vpp_se Vcm Vcm Vcm Figu...

Page 31: ... OUT7_CM 012D 3 0 OUT8_CM 0132 3 0 OUT9_CM 0137 3 0 OUT9A_CM 013C 3 0 8 4 4 LVCMOS Output Terminations LVCMOS outputs are dc coupled as shown in Figure 8 4 LVCMOS Output Terminations on page 31 3 3V 2 5V 1 8V LVCMOS VDDO 3 3V 2 5V 1 8V 50 Rs 50 Rs DC Coupled LVCMOS OUTx OUTx Figure 8 4 LVCMOS Output Terminations 8 4 5 LVCMOS Output Impedance and Drive Strength Selection Each LVCMOS driver has a co...

Page 32: ...3 7 6 OUT3_CMOS_DRV 0118 7 6 OUT4_CMOS_DRV 011D 7 6 OUT5_CMOS_DRV 0122 7 6 OUT6_CMOS_DRV 0127 7 6 OUT7_CMOS_DRV 012C 7 6 OUT8_CMOS_DRV 0131 7 6 OUT9_CMOS_DRV 0136 7 6 OUT9A_CMOS_DRV 013B 7 6 8 4 6 LVCMOS Output Signal Swing The signal swing VOL VOH of the LVCMOS output drivers is set by the voltage on the VDDO pins Each output driver has its own VDDO pin allowing a unique output voltage swing for ...

Page 33: ...when in LVCMOS mode Selections are as below in the Output Polarity Registers OUT0_INV 010B 7 6 OUT1_INV 0110 7 6 OUT2_INV 0115 7 6 OUT3_INV 011A 7 6 OUT4_INV 011F 7 6 OUT5_INV 0124 7 6 OUT6_INV 0129 7 6 OUT7_INV 012E 7 6 OUT8_INV 0133 7 6 OUT9_INV 0138 7 6 OUT9A_INV 013D 7 6 Table 8 9 Output Polarity of OUTx and OUTxb Pins in LVCMOS Mode OUTx_INV Register Settings OUTx OUTxb Comment 00 CLK CLK Bot...

Page 34: ...S LVPECL and HCSL on page 34 Table 8 10 Settings for LVDS LVPECL and HCSL OUTx_FORMAT1 Standard VDDO Volts OUTx_CM Decimal OUTx_AMPL Decimal 001 Normal Differential LVPECL 3 3 11 6 001 Normal Differential LVPECL 2 5 11 6 002 Low Power Differential LVPECL 3 3 11 3 002 Low Power Differential LVPECL 2 5 11 3 001 Normal Differential LVDS 3 3 3 3 001 Normal Differential LVDS 2 5 11 3 001 Normal Differe...

Page 35: ... signal for one receiver may be different than that of another receiver When the output amplitude needs to be different than standard LVDS or LVPECL the Common Mode Voltage settings must be set as shown in Table 8 11 Output Differential Common Mode Voltage Settings on page 35 No settings other than these are supported as the signal integrity could be compromised In addition the output driver shoul...

Page 36: ...FORMAT OUTx_CM and OUTx_AMPL Contact Skyworks for assistance if you require a factory programmed device to be configured for any of the output driver settings listed above Si5391 Reference Manual Outputs Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 36 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Cha...

Page 37: ...LL_DISABLE_LOW 0102 0 0 Disables all outputs 1 All outputs are not disabled by this signal but may be disabled by other signals or the OEB pin See figure above OUT0A_OE 0103 1 0 Specific output disabled 1 Specific output is not disabled The OEB pin or other signals within the device may be causing an output disable See figure above OUT0_OE 0108 1 OUT1_OE 010D 1 OUT2_OE 0112 1 OUT3_OE 0117 1 OUT4_O...

Page 38: ...e and will enable immediately without waiting a period to complete The default state is for the synchronous output disable enable to be turned on OUTx_SYNC_EN 1 Table 8 14 Synchronous Disable Control Registers Setting Name Hex Address Bit Field Function Si5391 Si5391P OUT0A_SYNC_EN 0104 3 When this bit is high the output will turn on off enable disable without generating runt pulses or glitches Th...

Page 39: ... Tvco of 71 43 psec The skew value may change after each reset or power cycle Table 8 16 Input Output Skew Control Registers Type Setting Names Setting Address Start Typical Resolution Dynamic Nx_PHASE_STEP Nx_PHASE_COUNT 0x0A38 TVCO 71 43 ps For more details on how these registers are enabled and programmed see the appropriate register map section toward the end of this reference manual Si5391 Re...

Page 40: ...or this reason ClockBuilder Pro will not enable Zero Delay Mode with an Fpfd of less than 128 kHz When the DSPLL is set for Zero Delay Mode ZDM a hard reset request from either the RSTb pin or RST_REG register bit will have a delay of 750 ms before executing Any subsequent register writes to the device should be made after this time expires or they will be overwritten with the NVM values Please co...

Page 41: ... it may be necessary to adjust the Nx_NUM value while keeping the ratio of Nx_NUM Nx_DEN the same When the FINC or FDEC pin or register bit is asserted the selected N dividers will have their numerator changed by the addition or subtraction of the Nx_FSTEPW so that an FINC will increase the output frequency and an FDEC will decrease the output frequency An FINC or FDEC can be followed by another F...

Page 42: ... SDI SDO CSb CSb SDO SDI SCLK SCLK Clock IC I2 C HOST 1 8V VDDA SCLK SDA 1 8V VDD 1 8V 3 3V SPI HOST 1 8V SDIO SDIO CSb CSb SCLK SCLK SPI_3WIRE 0 SPI 4 Wire SPI 3 Wire I2C_SEL pin Low SPI_3WIRE 1 IO_VDD_SEL 0 IO_VDD_SEL 1 IO_VDD_SEL 1 IO_VDD_SEL 1 SCLK SDA Default Default VDDA VDD 1 8V 3 3V Default VDDA VDD 1 8V 3 3V SPI HOST 3 3V SDI SDO CSb CSb SDO SDI SCLK SCLK I2 C HOST 3 3V VDDA SCLK SDA 3 3V...

Page 43: ... the host and the serial interface are operating at the optimum voltage thresholds SPI_3WIRE 0x002B 3 The SPI_3WIRE configuration bit selects the option of 4 wire or 3 wire SPI communication By default this configuration bit is set to the 4 wire option In this mode the Si5391 Si5391P will accept write commands from a 4 wire or 3 wire SPI host allowing config uration of device registers For full bi...

Page 44: ...re 11 3 7 bit I2C Slave Address Bit Configuration Data is transferred MSB first in 8 bit words as specified by the I2C specification A write command consists of a 7 bit device slave address a write bit an 8 bit register address and 8 bits of data as shown in Figure 11 6 SPI Interface Connections on page 46 A write burst operation is also shown where subsequent data words are written using to an au...

Page 45: ...on The SMBUS interface requires a timeout The error flags are found in the registers listed below Table 11 2 SMBus Timeout Error Bit Indicators Register Name Hex Address Bit Field Function SMBUS_TIMEOUT 0x000C 5 1 if there is a SMBus timeout error SMBUS_TIME OUT_FLG 0x0011 5 1 if there is a SMBus timeout error Si5391 Reference Manual Serial Interface Skyworks Solutions Inc Phone 781 376 3000 Fax 7...

Page 46: ...mand but the address will wrap around to zero in the byte after address 255 is written Writing or reading data consist of sending a Set Address command followed by a Write Data or Read Data command The Write Data Address Increment or Read Data Address Increment commands are available for cases where multiple byte operations in sequential address locations is necessary The Burst Write Data instruct...

Page 47: ...s Set Address and Read Data Address Increment Set Address and Read Data Set Addr Addr 7 0 Read Data Data 7 0 Set Addr Addr 7 0 Read Data Data 7 0 Set Addr Addr 7 0 Read Data Data 7 0 Data 7 0 Set Addr Addr 7 0 Data 7 0 Clock IC Host Clock IC Host Read Data Addr Inc Read Data Addr Inc Data 7 0 Read Data Addr Inc Figure 11 8 Example of Reading Three Data Bytes Using the SPI Read Commands Si5391 Refe...

Page 48: ...s Instruction Base Address CS SCLK SDI SDO SDIO 4 Wire 3 Wire Set Address Command 95 ns Previous Command Next Command 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 6 7 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 6 7 Clock IC Host Clock IC Host Don t Care High Impedance 7 7 95 ns Figure 11 9 SPI Set Address Command Timing Si5391 Reference Manual Serial Interface Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100...

Page 49: ...7 6 7 Clock IC Host Clock IC Host Don t Care High Impedance 95 ns 95 ns Figure 11 10 SPI Write Data and Write Data Address Increment Instruction Timing Si5391 Reference Manual Serial Interface Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 49 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Change Without...

Page 50: ...1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Clock IC Host Clock IC Host Don t Care High Impedance 1st data byte base address 6 Next Command 6 7 7 7 7 7 7 7 95 ns 95 ns Figure 11 12 SPI Burst Data Write Instruction Timing Note that for all SPI communication the chip select CS must be high for the minimum time period between commands When chip select goes high it indicates the terminatio...

Page 51: ... reference devices only Layer 3 ground plane Layer 4 power distribution Layer 5 power routing layer Layer 6 input clocks Layer 7 output clocks layer Layer 8 ground layer The 64 pin QFN crystal guidelines show the top layer layout of the Si5391 Si5391P device mounted on the top PCB layer This particular layout was designed to implement either a crystal or an external oscillator as the XAXB referenc...

Page 52: ...r Layer 2 on page 53 4 Minimize traces adjacent to the crystal oscillator area especially if they are clocks or frequently toggling digital signals 5 In general do not route GND power planes traces or locate components on the other side below the crystal GND shield As an exception if it is absolutely necessary to use the area on the other side of the board for layout or routing then place the next...

Page 53: ...e a ground shield above below and on the sides for protection Figure 12 3 Crystal Ground Plane Layer 3 on page 54 is the ground plane and shows a void underneath the crystal shield Figure 12 4 Power Plane Layer 4 on page 55 is a power plane and shows the clock output power supply traces The void underneath the crystal shield is continued Si5391 Reference Manual Crystal XO and Device Circuit Layout...

Page 54: ... and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 54 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice January 11 2022 54 ...

Page 55: ...wer routed to the clock output power pins Si5391 Reference Manual Crystal XO and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 55 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice January 11 2022 55 ...

Page 56: ...imilar to layer 3 Si5391 Reference Manual Crystal XO and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 56 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice January 11 2022 56 ...

Page 57: ... Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 57 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice January 11 2022 57 ...

Page 58: ...a line of vias through the ground flood on either side of the output clocks to ensure that the ground flood immediately next to the differential pairs has a low inductance path to the ground plane on layers 3 and 6 Figure 12 7 Output Clock Layer Layer 7 Si5391 Reference Manual Crystal XO and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyw...

Page 59: ...l XO and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 59 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice January 11 2022 59 ...

Page 60: ...llator and buffer circuitry at the XA XB pins 1 No power down 13 2 Power Supply Recommendations The power supply filtering generally is important for optimal timing performance The Si5391 Si5391P devices have multiple stages of on chip regulation to minimize the impact of board level noise on clock jitter Following conventional power supply filtering and layout techniques will further minimize sig...

Page 61: ...owered down first then it will not drop far below VDD until VDD itself is powered down This is due to the pad I O circuits which have large MOSFET switches to select the local supply from either the VDD or VDDA rails These devices are relatively large and yield a parasitic diode between VDD and VDDA Please allow for both VDD and VDDA to power up and power down before measuring their respective vol...

Page 62: ...grammed for a particular application that includes specifying the XA XB reference frequency type the clock input frequencies the clock output frequencies as well as the other options such as automatic clock selection loop BW etc The ClockBuilder software is required to select among all of these options and to produce a project file which Skyworks uses to preprogram all devices with custom orderabl...

Page 63: ...nformation are organized hierarchically below To find the relevant information for your application first choose the section corresponding to the base part number Si5391 for your design Then choose the section under that for the page containing the desired register s Default register contents and settings differ for each device part number or OPN This information may be found by searching for the ...

Page 64: ...7 0 R PN_BASE Four digit base part number one nibble per digit Example Si5391A A GM The base part number OPN is 5391 which is stored in this register 0x0003 15 8 R PN_BASE Table 15 4 0x0004 Device Speed Synthesis Mode Grade Reg Address Bit Field Type Setting Name Description 0x0004 7 0 R GRADE One ASCII character indicating the device speed grade 0 A 1 B 2 C 3 D 15 P Table 15 5 0x0005 Device Revis...

Page 65: ...lder Pro Table 15 8 0x000B I2C Address Reg Address Bit Field Type Setting Name Description 0x000B 6 2 R W I2C_ADDR The upper 5 bits of the 7 bit I2C address The lower 2 bits are controlled by the A1 and A0 pins Table 15 9 0x000C Status Bits Reg Address Bit Field Type Setting Name Description 0x000C 0 R SYSINCAL 1 if the device is calibrating 0x000C 1 R LOSXAXB 1 if there is no signal at the XA pin...

Page 66: ...it Field Type Setting Name Description 0x0017 0 R W SYSINCAL_INTR_MSK 1 to mask SYSINCAL_FLG from causing an interrupt 0x0017 1 R W LOSXAXB_INTR_MSK 1 to mask the LOSXAXB_FLG from causing an interrupt 0x0017 2 R W LOSREF_INTR_MSK 1 to mask LOSREF_FLG from causing an interrupt 0x0017 3 R W LOL_INTR_MSK 1 to mask LOL_FLG from causing an interrupt 0x0017 5 R W SMB_TMOUT_INTR_MSK 1 to mask SMBUS_TIMEO...

Page 67: ...to low power mode 0x001E 1 R W HARD_RST 1 causes hard reset The same as power up except that the serial port access is not held at reset NVM is re downloaded This does not self clear so after setting the bit it must be cleared 0 No reset 0x001E 2 S SYNC 1 to reset all output R dividers to the same state Table 15 18 0x0021 Input Clock Selection Reg Address Bit Field Type Setting Name Description 0x...

Page 68: ...fore has an active LOS alarm if the clock returns there is a period of time that the clock must be within the acceptable range before the alarm is removed This is the LOS_VAL_TIME Table 15 22 0x002E 0x002F LOS0 Trigger Threshold Reg Address Bit Field Type Setting Name Description 0x002E 7 0 R W LOS0_TRG_THR 16 bit Threshold Value 0x002F 15 8 R W LOS0_TRG_THR ClockBuilder Pro calculates the correct...

Page 69: ...r Threshold Reg Address Bit Field Type Setting Name Description 0x0038 7 0 R W LOS1_CLR_THR 16 bit Threshold Value 0x0039 15 8 R W LOS1_CLR_THR ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 1 given a particular frequency plan Table 15 28 0x003A 0x003B LOS2 Clear Threshold Reg Address Bit Field Type Setting Name Description 0x003A 7 0 R W LOS2_CLR_THR 16 bit T...

Page 70: ...ollowing are the pre divider values for the above listed registers values Register Value Decimal Divider Value 0 1 bypass 1 2 2 4 3 8 4 16 5 32 6 64 7 128 8 256 9 512 10 1024 11 2048 12 4096 13 8192 14 16384 15 32768 16 65536 Table 15 31 0x009E Reg Address Bit Field Type Setting Name Description 0x009E 7 4 R W LOL_SET_THR Configures the loss of lock set thresholds Si5391 Reference Manual Si5391A B...

Page 71: ...is bit will read the NVM down into the vola tile memory Table 15 35 0x00F6 Reg Address Bit Field Type Setting Name Description 0x00F6 0 R REG_0XF7_INTR Set by CBPro 0x00F6 1 R REG_0XF8_INTR Set by CBPro 0x00F6 2 R REG_0XF9_INTR Set by CBPro Table 15 36 0x00F7 Reg Address Bit Field Type Setting Name Description 0x00F7 0 R SYSINCAL_INTR Set by CBPro 0x00F7 1 R LOSXAXB_INTR Set by CBPro 0x00F7 2 R LO...

Page 72: ...hen read data is 0x0F one can safely read write registers This register is repeated on every page therefore a page write is not ever required to read the DEVICE_READY status Si5391 Reference Manual Si5391A B Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 72 Rev 0 5 Skyworks Proprietary Information Products and Product Information a...

Page 73: ...lt 1 Divide value forced to divide by 2 Setting R0A_REG 0 will not set the divide value to divide by 2 automatically OUT0A_RDIV_FORCE2 must be set to a value of 1 to force R0A to divide by 2 Note that the R0A_REG value will be ignored while OUT0A_RDIV_FORCE2 1 See R0A_REG registers 0x0247 0x0249 for more information Table 15 41 0x0104 Clock Output 0A Format Reg Address Bit Field Type Setting Name ...

Page 74: ...is field only applies when OUT0A_FORMAT 1 or 2 See 8 4 8 Output Driver Settings for LVPECL LVDS HCSL and CML and 8 4 9 Setting the Differential Out put Driver to Non Standard Amplitudes for details of the settings ClockBuilder Pro sets the correct common mode voltage and amplitude for LVDS LVPECL and HCSL outputs Table 15 43 0x0106 Clock Output 0A Mux and Inversion Reg Address Bit Field Type Setti...

Page 75: ...T0_VDD_SEL OUT0_INV 0x0106 0x010D OUT1_PDN OUT1_OE OUT1_RDIV_FORCE2 0x0103 0x010E OUT1_FORMAT _SYNC_EN DIS_STATE _CMOS_DRV 0x0104 0x010F OUT1_CM OUT1_AMPL 0x0105 0x0110 OUT1_MUX_SEL OUT1_VDD_SEL_EN OUT1_VDD_SEL OUT1_INV 0x0106 0x0112 OUT2_PDN OUT2_OE OUT2_RDIV_FORCE2 0x0103 0x0113 OUT2_FORMAT _SYNC_EN DIS_STATE _CMOS_DRV 0x0104 0x0114 OUT2_CM OUT2_AMPL 0x0104 0x0115 OUT2_MUX_SEL OUT2_VDD_SEL_EN OU...

Page 76: ...136 OUT9_FORMAT _SYNC_EN DIS_STATE _CMOS_DRV 0x0104 0x0137 OUT9_CM OUT9_AMPL 0x0105 0x0138 OUT9_MUX_SEL OUT9_VDD_SEL_EN OUT9_VDD_SEL OUT9_INV 0x0106 0x013A OUT9A_PDN OUT9A_OE OUT9A_RDIV_FORCE2 0x0103 0x013B OUT9A_FORMAT _SYNC_EN DIS_STATE _CMOS_DRV 0x0104 0x013C OUT9A_CM OUT9A_AMPL 0x0105 0x013D OUT9A_MUX_SEL OUT9A_VDD_SEL_EN OUT9A_VDD_SEL OUT9A_INV 0x0106 Table 15 45 0x013F 0x0140 Reg Address Bit...

Page 77: ... 0 no effect 1 all drivers powered down Si5391 Reference Manual Si5391A B Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 77 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice January 11 2022 77 ...

Page 78: ...g registers configure the P dividers which are located at the four input clocks seen in 3 1 Dividers ClockBuilder Pro calculates the correct values for the P dividers The Px_Update register 0x0230 bit for the appropriate channel must be updated for the new P value to take affect Table 15 50 0x0208 0x020D P0 Dividers Reg Address Bit Field Type Setting Name Description 0x0208 7 0 R W P0 48 bit Integ...

Page 79: ...eg Address Bit Field Type Setting Name Description 0x021C 7 0 R W P2 48 bit Integer Number 0x021D 15 8 R W P2 0x021E 23 16 R W P2 0x021F 31 24 R W P2 0x0220 39 32 R W P2 0x0221 47 40 R W P2 Table 15 55 0x0222 0x0225 P2 Divider Enable Set Reg Address Bit Field Type Setting Name Description 0x0222 7 0 R W P2_SET Set by CBPro 0x0223 15 8 R W P2_SET 0x0224 23 16 R W P2_SET 0x0225 31 24 R W P2_SET Si53...

Page 80: ...this bit to cause a change to the P1 divider to take effect 0x0230 2 S P2_UPDATE Must write a 1 to this bit to cause a change to the P2 divider to take effect 0x0230 3 S P3_UPDATE Must write a 1 to this bit to cause a change to the P3 divider to take effect Bits 7 4 of this register have no function and can be written to any value Table 15 59 0x0235 0x023A M Divider Numerator Reg Address Bit Field...

Page 81: ...w the formula in the bit description above divide by 2 requires an extra bit to be set For divide by 2 set OUT0A_RDIV_FORCE2 1 See the description for register bit 0x0103 2 in this register map The R0 R9A dividers follow the same format as the R0A divider description above Table 15 63 R Dividers for Outputs 0 1 2 3 4 5 6 7 8 9 9A Register Address Setting Name Size Same as Address 0x024A 0x024C R0_...

Page 82: ...nique identifier ASCII encoded For example with OPN 5391C A12345 GM 12345 is the OPN unique identifier which sets OPN_ID0 0x31 OPN_ID1 0x32 OPN_ID2 0x33 OPN_ID3 0x34 OPN_ID4 0x35 0x0279 15 8 R W OPN_ID1 0x027A 23 16 R W OPN_ID2 0x027B 31 24 R W OPN_ID3 0x027C 39 32 R W OPN_ID4 Part numbers are of the form Si Part Num Base Grade Device Revision OPN ID Temp Grade Package ID Examples Si5391C A12345 G...

Page 83: ...ess Bit Field Type Setting Name Description 0x027E 7 0 R W BaseLine ID An identifier for the device NVM without the frequency plan programmed into NVM Si5391 Reference Manual Si5391A B Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 83 Rev 0 5 Skyworks Proprietary Information Products and Product Information are Subject to Change Wi...

Page 84: ...er changes to take effect This bit is provided so that all of the N0 divider bits can be changed at the same time First write all of the new values to the divider then set the update bit Table 15 71 N1 N2 N3 Numerator and Denominators Register Address Setting Name Size Same as Address 0x030D 0x0312 N1_NUM 44 bit Integer Number 0x0302 0x0307 0x0313 0x0316 N1_DEN 32 bit Integer Number 0x0308 0x030B ...

Page 85: ...y writing a 1 to this bit When this bit is written to a 1 all other bits in this byte should only be written to a 0 This bit is provided so that all of the divider bits can be changed at the same time First write all of the new values to the divider then set the update bit Note If the intent is to write to the N_UPDATE_ALL to have all dividers update at the same time then make sure only bit 1 N_UP...

Page 86: ...value The Nx_NUM register value does not change when an FINC or FDEC is performed so that the starting point of Nx_NUM is in the Nx_NUM register Table 15 79 Frequency Step Word for N1 N2 N3 N4 Register Address Setting Name Size Same as Address 0x0341 0x0346 N1_FSTEPW 44 bit Integer Number 0x033B 0x0340 0x0347 0x034C N2_FSTEPW 44 bit Integer Number 0x033B 0x0340 0x034D 0x0352 N3_FSTEPW 44 bit Integ...

Page 87: ... and the Si5391 IO_VDD_SEL 1 8 V the host should write the IO_VDD_SEL configuration bit to the VDDA option This will ensure that both the host and the serial interface are operating at the optimum voltage thresholds The IO_VDD_SEL bit also affects the status pin levels and control pin thresholds When IO_VDD_SEL 0 the status outputs will have a VOH of 1 8 V When IO_VDD_SEL 1 the status outputs will...

Page 88: ...0 IN_SEL is used to select the input clock that is applied to the phase detector Table 15 85 0x095E Reg Address Bit Field Type Setting Name Description 0x095E 0 R W M_INTEGER Set by CBPro Si5391 Reference Manual Si5391A B Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 88 Rev 0 5 Skyworks Proprietary Information Products and Product...

Page 89: ...ations with Jitter Attenuators Table 15 88 0x0A05 N Divider Power Down Reg Address Bit Field Type Name Description 0x0A05 4 0 R W N_PDNB Powers down the N divider If an N divider is not used set the respective bit to 0 to power it down Bits in this field correspond to the N dividers as N4 N3 N2 N1 N0 See also registers 0x0A03 and 0x0B4A 4 0 Table 15 89 0x0A38 N0 Dynamic Phase Adjust Step Size Reg ...

Page 90: ... 0 R W N1_PHASE_INC Writing a 1 initiates a phase increment 0x0A3F 1 R W N1_PHASE_DEC Writing a 1 initiates a phase decrement N2 dynamic phase adjust works the same as N0 dynamic phase adjust 0xA38 Table 15 95 0x0A40 N2 Dynamic Phase Adjust Step Size Reg Address Bit Field Type Name Description 0x0A40 7 0 R W N2_PHASE_STEP N2 step size from 1 to 255 in units of Tvco the VCO period Table 15 96 0x0A4...

Page 91: ...8 7 0 R W N4_PHASE_STEP N4 step size from 1 to 255 in units of Tvco the VCO period Table 15 102 0x0A49 N4 Dynamic Phase Adjust Step Size Count Reg Address Bit Field Type Name Description 0x0A49 7 0 R W N4_PHASE_COUNT Lower byte of number of N4 step size changes 0x0A4A 15 8 R W N4_PHASE_COUNT Upper byte of number of N4 step size changes Table 15 103 0x0AB N4 Dynamic Phase Adjust Command Reg Address...

Page 92: ...Address Bit Field Type Setting Name Description 0x0B4A 4 0 R W N_CLK_DIS Controls the clock to the N divider If an N divider is used the corresponding bit must be 0 N3 N2 N1 N0 See also registers 0x0A03 and 0x0A05 Table 15 107 0x0B57 Reg Address Bit Field Type Name Description 0x0B57 7 0 R W VCO_RESET_CAL CODE 12 bit value 0x0B58 11 8 R W VCO_RESET_CAL CODE Si5391 Reference Manual Si5391A B Regist...

Page 93: ...table 16 49 for registers 0x013F and 0x0140 Description and type added for P0 P1 P2 and P3 divider Enable Set tables Description added for table 16 59 for M divider numerator Changes made to R divider register tables 16 62 and 16 63 to include OUT0A and OUT9A Text below tabl 16 62 updated Text added below Table 16 65 to indicate User Scratch Text added below table 16 76 about register 0x0338 Remov...

Page 94: ...CLUDING WITHOUT LIMITATION LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Skyworks products are not intended for use in medical lifesaving or life sustaining applications or other equipment in which the failure of the Skyworks products could lead to personal inju...

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