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Silicon Laboratories Si8410 Manual Download Page 23

Rev. 1.1

23

S i 8 4 1 0 / 2 0 / 2 1   ( 5   k V )

S i 8 4 2 2 / 2 3   ( 2 . 5   &   5   k V )

3.1.  Device Startup

Outputs are held low during powerup until 

V

DD

 is above the UVLO threshold for time period tSTART. Following this,

the outputs follow the states of inputs.

3.2.  Under Voltage Lockout

Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when 

V

DD

 is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage

lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters
UVLO when V

DD1

 falls below V

DD1(UVLO–)

 and exits UVLO when V

DD1

 rises above V

DD1(UVLO+)

. Side B operates

the same as Side A with respect to its V

DD2

 supply.

Figure 7. Device Behavior during Normal Operation

INPUT

V

DD1

UVLO-

V

DD2

UVLO+

UVLO-

UVLO+

OUTPUT

tSTART

tSTART

tSTART

tPHL

tPLH

tSD

Summary of Contents for Si8410

Page 1: ...d by UL CSA and VDE and products in wide body packages support reinforced insulation withstanding up to 5 kVRMS High speed operation DC to 150 Mbps No start up initialization required Wide Operating Supply Voltage 2 6 5 5 V Up to 5000 VRMS isolation High electromagnetic immunity Ultra low power typical 5 V Operation 2 6 mA channel at 1 Mbps 6 8 mA channel at 100 Mbps 2 70 V Operation 2 3 mA channe...

Page 2: ...Si8410 20 21 5 kV Si8422 23 2 5 5 kV 2 Rev 1 1 ...

Page 3: ...ations 24 3 4 Fail Safe Operating Mode 24 3 5 Typical Performance Characteristics 25 4 Pin Descriptions Wide Body SOIC 27 5 Pin Descriptions Narrow Body SOIC 28 6 Ordering Guide 29 7 Package Outline 16 Pin Wide Body SOIC 30 8 Land Pattern 16 Pin Wide Body SOIC 31 9 Package Outline 8 Pin Narrow Body SOIC 32 10 Land Pattern 8 Pin Narrow Body SOIC 33 11 Top Marking 16 Pin Wide Body SOIC 34 12 Top Mar...

Page 4: ...All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC 1 3 1 7 5 8 1 7 2 0 2 6 8 7 2 6 mA Si8421Ax Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC 1 7 1 7 3 7 3 7 2 6 2 6 5 6 5 6 mA Si8422Ax Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC 3 7 3 7 1 7 1 7 5 6 5 6 2 6 2 6 mA Si8423Ax Bx VDD1 VDD2 VDD1 VDD2 All inp...

Page 5: ... 5 5 1 3 5 mA Table 1 Electrical Characteristics Continued VDD1 5 V 10 VDD2 5 V 10 TA 40 to 125 ºC Parameter Symbol Test Condition Min Typ Max Unit Notes 1 The nominal output impedance of an isolator driver channel is approximately 50 40 which is a combination of the value of the on chip series termination resistor and channel resistance of the output driver FET When driving loads where transmissi...

Page 6: ... Channel Skew tPSK 0 5 1 5 ns All Models Output Rise Time tr CL 15 pF 2 0 4 0 ns Output Fall Time tf CL 15 pF 2 0 4 0 ns Peak Eye Diagram Jitter tJIT PK See Figure 6 350 ps Common Mode Transient Immunity CMTI VI VDD or 0 V 20 45 kV µs Start up Time3 tSU 15 40 µs Table 1 Electrical Characteristics Continued VDD1 5 V 10 VDD2 5 V 10 TA 40 to 125 ºC Parameter Symbol Test Condition Min Typ Max Unit Not...

Page 7: ...Rev 1 1 7 Si8410 20 21 5 kV Si8422 23 2 5 5 kV Figure 1 Propagation Delay Timing Typical Input tPLH tPHL Typical Output tr tf 90 10 90 10 1 4 V 1 4 V ...

Page 8: ...uts 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC 1 3 1 7 5 8 1 7 2 0 2 6 8 7 2 6 mA Si8421Ax Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC 1 7 1 7 3 7 3 7 2 6 2 6 5 6 5 6 mA Si8422Ax Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC 3 7 3 7 1 7 1 7 5 6 5 6 2 6 2 6 mA Si8423Ax Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 D...

Page 9: ...2 5 1 3 1 mA Table 2 Electrical Characteristics Continued VDD1 3 3 V 10 VDD2 3 3 V 10 TA 40 to 125 C Parameter Symbol Test Condition Min Typ Max Unit Notes 1 The nominal output impedance of an isolator driver channel is approximately 50 40 which is a combination of the value of the on chip series termination resistor and channel resistance of the output driver FET When driving loads where transmis...

Page 10: ...s Pulse Width Distortion tPLH tPHL PWD See Figure 1 1 5 3 0 ns Propagation Delay Skew2 tPSK P P 2 0 3 0 ns Channel Channel Skew tPSK 0 5 1 5 ns Table 2 Electrical Characteristics Continued VDD1 3 3 V 10 VDD2 3 3 V 10 TA 40 to 125 C Parameter Symbol Test Condition Min Typ Max Unit Notes 1 The nominal output impedance of an isolator driver channel is approximately 50 40 which is a combination of the...

Page 11: ... The nominal output impedance of an isolator driver channel is approximately 50 40 which is a combination of the value of the on chip series termination resistor and channel resistance of the output driver FET When driving loads where transmission line effects will be a factor output pins should be appropriately terminated with controlled impedance PCB traces 2 tPSK P P is the magnitude of the dif...

Page 12: ... 6 8 7 2 6 mA Si8421Ax Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC 1 7 1 7 3 7 3 7 2 6 2 6 5 6 5 6 mA Si8422Ax Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC 3 7 3 7 1 7 1 7 5 6 5 6 2 6 2 6 mA Si8423Ax Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC 5 4 1 7 1 3 1 7 8 1 2 6 2 0 ...

Page 13: ... VDD2 2 70 V TA 40 to 125 C Parameter Symbol Test Condition Min Typ Max Unit Notes 1 Specifications in this table are also valid at VDD1 2 6 V and VDD2 2 6 V when the operating temperature range is constrained to TA 0 to 85 C 2 The nominal output impedance of an isolator driver channel is approximately 50 40 which is a combination of the value of the on chip series termination resistor and channel...

Page 14: ...tion Delay Skew3 tPSK P P 2 0 3 0 ns Channel Channel Skew tPSK 0 5 1 5 ns Table 3 Electrical Characteristics1 Continued VDD1 2 70 V VDD2 2 70 V TA 40 to 125 C Parameter Symbol Test Condition Min Typ Max Unit Notes 1 Specifications in this table are also valid at VDD1 2 6 V and VDD2 2 6 V when the operating temperature range is constrained to TA 0 to 85 C 2 The nominal output impedance of an isolat...

Page 15: ...ditions as specified in the operational sections of this data sheet 2 VDE certifies storage temperature from 40 to 150 C Table 3 Electrical Characteristics1 Continued VDD1 2 70 V VDD2 2 70 V TA 40 to 125 C Parameter Symbol Test Condition Min Typ Max Unit Notes 1 Specifications in this table are also valid at VDD1 2 6 V and VDD2 2 6 V when the operating temperature range is constrained to TA 0 to 8...

Page 16: ...voltage up to 1000 VRMS basic insulation working volt age 60601 1 Up to 125 VRMS reinforced insulation working voltage up to 380 VRMS basic insulation working voltage VDE The Si84xx is certified according to IEC 60747 5 2 For more details see File 5006301 4880 0001 60747 5 2 Up to 891 Vpeak for basic insulation working voltage 60950 1 Up to 600 VRMS reinforced insulation working voltage up to 1000...

Page 17: ... limits as 8 5 mm minimum for the WB SOIC 16 package and 4 7 mm minimum for the NB SOIC 8 package UL does not impose a clearance and creepage minimum for component level certifications CSA certifies the clearance and creepage limits as 3 9 mm minimum for the NB SOIC 8 and 7 6 mm minimum for the WB SOIC 16 package 2 To determine resistance and capacitance the Si84xx is converted into a 2 terminal d...

Page 18: ...tance at TS VIO 500 V RS 109 109 Note Maintenance of the safety data is ensured by protective circuits The Si84xx provides a climate classification of 40 125 21 Table 10 IEC Safety Limiting Values1 Parameter Symbol Test Condition Min Typ Max Unit WB SOIC 16 NB SOIC 8 Case Temperature TS 150 150 C Safety Input Output or Supply Current IS JA 140 C W NB SOIC 8 100 C WB SOIC 16 VI 5 5 V TJ 150 C TA 25...

Page 19: ...th Case Temperature per DIN EN 60747 5 2 Table 11 Thermal Characteristics Parameter Symbol WB SOIC 16 NB SOIC 8 Unit IC Junction to Air Thermal Resistance JA 100 140 ºC W 0 200 150 100 50 500 250 125 0 Case Temperature ºC Safety Limiting Values mA 460 375 VDD1 VDD2 2 70 V VDD1 VDD2 3 3 V VDD1 VDD2 5 5 V 360 220 0 200 150 100 50 400 200 100 0 Case Temperature ºC Safety Limiting Values mA 320 300 VD...

Page 20: ...er and RF Receiver separated by a semiconductor based isolation barrier Referring to the Transmitter input A modulates the carrier provided by an RF oscillator using on off keying The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver This RF on off keying scheme is superior to pulse code schemes ...

Page 21: ...ritsu MP1763C Pulse Pattern Generator set to 1000 ns div The output of the generator s clock and data from an Si8422 were captured on an oscilloscope The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited Figure 6 Eye Diagram ...

Page 22: ...e same state as VI in less than 1 µs X5 P UP Undetermined Upon transition of VDDO from unpowered to powered VO returns to the same state as VI within 1 µs Notes 1 VDDI and VDDO are the input and output power supplies VI and VO are the respective input and output terminals 2 Powered P state is defined as 2 70 V VDD 5 5 V 3 Unpowered UP state is defined as VDD 0 V 4 X not applicable H Logic High L L...

Page 23: ...vice startup and shutdown or when VDD is below its specified operating circuits range Both Side A and Side B each have their own undervoltage lockout monitors Each side can enter or exit UVLO independently For example Side A unconditionally enters UVLO when VDD1 falls below VDD1 UVLO and exits UVLO when VDD1 rises above VDD1 UVLO Side B operates the same as Side A with respect to its VDD2 supply F...

Page 24: ...3 1 Supply Bypass The Si841x 2x family requires a 0 1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2 The capacitor should be placed as close as possible to the package To enhance the robustness of a design it is further recommended that the user also add 1 µF bypass capacitors and include 100 resistors in series with the inputs and outputs if the system is excessively noisy 3 3 2 Pin ...

Page 25: ...l VDD2 Supply Current vs Data Rate 5 3 3 and 2 70 V Operation 15 pF Load Figure 13 Si8422 Typical VDD1 or VDD2 Supply Current vs Data Rate 5 3 3 and 2 70 V Operation 15 pF Load 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate Mbps Current mA 5V 3 3V 2 70V 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate Mbps Current mA 5V 3 3V 2 70V...

Page 26: ...3 and 2 70 V Operation 15 pF Load Figure 16 Propagation Delay vs Temperature 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate Mbps Current mA 5V 3 3V 2 70V 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate Mbps Current mA 5V 2 70V 3 3V 5 6 7 8 9 10 40 20 0 20 40 60 80 100 120 Temperature Degrees C Delay ns Rising Edge Falling Edge ...

Page 27: ... input or output VDD2 14 14 Supply Side 2 power supply GND2 16 16 Ground Side 2 ground Note No Connect These pins are not internally connected They can be left floating tied to VDD or tied to GND GND1 NC A1 VDD1 GND2 B1 NC GND2 I s o l a t i o n RF XMITR RF RCVR NC GND1 NC NC VDD2 NC Si8410 WB SOIC 16 NC NC GND1 A2 NC A1 VDD1 GND2 B1 NC B2 GND2 I s o l a t i o n RF XMITR RF RCVR RF XMITR RF RCVR N...

Page 28: ...utput A2 3 Digital I O Side 1 digital input or output B1 7 Digital I O Side 2 digital input or output B2 6 Digital I O Side 2 digital input or output VDD2 8 Supply Side 2 power supply GND2 5 Ground Side 2 ground I s o l a t i o n VDD1 VDD2 A1 B1 A2 B2 RF XMITR RF RCVR GND1 GND2 Si8422 NB SOIC 8 RF RCVR RF XMITR RF RCVR RF XMITR I s o l a t i o n VDD1 VDD2 A1 B1 RF XMITR RF RCVR A2 B2 RF XMITR RF R...

Page 29: ...OIC 16 Si8410BD A IS2 1 0 150 Low Si8420AD A IS2 2 0 1 Low Si8420BD A IS2 2 0 150 Low Si8421AD B IS2 1 1 1 Low Si8421BD B IS2 1 1 150 Low Si8422AD B IS 1 1 1 High Si8422BD B IS 1 1 150 High Si8423AD B IS 2 0 1 High Si8423BD B IS 2 0 150 High Notes 1 All packages are RoHS compliant with peak reflow temperatures of 260 C according to the JEDEC industry standard classifications and peak solder temper...

Page 30: ...ge details for the Si84xx Digital Isolator Table 14 lists the values for the dimensions shown in the illustration Figure 17 16 Pin Wide Body SOIC Table 14 Package Diagram Dimensions Symbol Millimeters Min Max A 2 65 A1 0 1 0 3 D 10 3 BSC E 10 3 BSC E1 7 5 BSC b 0 31 0 51 c 0 20 0 33 e 1 27 BSC h 0 25 0 75 L 0 4 1 27 0 7 ...

Page 31: ...stration Figure 18 16 Pin SOIC Land Pattern Table 15 16 Pin Wide Body SOIC Land Pattern Dimensions Dimension Feature mm C1 Pad Column Spacing 9 40 E Pad Row Pitch 1 27 X1 Pad Width 0 60 Y1 Pad Length 1 90 Notes 1 This Land Pattern Design is based on IPC 7351 pattern SOIC127P1032X265 16AN for Density Level B Median Land Protrusion 2 All feature sizes shown are at Maximum Material Condition MMC and ...

Page 32: ...4xx Table 16 lists the values for the dimensions shown in the illustration Figure 19 8 pin Small Outline Integrated Circuit SOIC Package Table 16 Package Diagram Dimensions Symbol Millimeters Min Max A 1 35 1 75 A1 0 10 0 25 A2 1 40 REF 1 55 REF B 0 33 0 51 C 0 19 0 25 D 4 80 5 00 E 3 80 4 00 e 1 27 BSC H 5 80 6 20 h 0 25 0 50 L 0 40 1 27 0 8 ...

Page 33: ...n Figure 20 PCB Land Pattern 8 Pin Narrow Body SOIC Table 17 PCM Land Pattern Dimensions 8 Pin Narrow Body SOIC Dimension Feature mm C1 Pad Column Spacing 5 40 E Pad Row Pitch 1 27 X1 Pad Width 0 60 Y1 Pad Length 1 55 Notes 1 This Land Pattern Design is based on IPC 7351 pattern SOIC127P600X173 8N for Density Level B Median Land Protrusion 2 All feature sizes shown are at Maximum Material Conditio...

Page 34: ...reverse channels 1 0 1 2 S Speed Grade A 1 Mbps B 150 Mbps V Insulation rating A 1 kV B 2 5 kV C 3 75 kV D 5 kV Line 2 Marking YY Year WW Workweek Assigned by assembly subcontractor Corresponds to the year and workweek of the mold date TTTTTT Mfg Code Manufacturing code from assembly house Line 3 Marking Circle 1 5 mm Diameter Center Justified e3 Pb Free Symbol Country of Origin ISO Code Abbreviat...

Page 35: ...ade A 1 Mbps B 150 Mbps V Insulation rating A 1 kV B 2 5 kV C 3 75 kV D 5 kV Line 2 Marking YY Year WW Workweek Assigned by assembly subcontractor Corresponds to the year and workweek of the mold date R Product OPN Revision F Wafer Fab Line 3 Marking Circle 1 1 mm Diameter Left Justified e3 Pb Free Symbol First two characters of the manufacturing code A Assembly Site I Internal Code XX Serial Lot ...

Page 36: ...Diagram jitter in Tables 1 2 and 3 Updated transient immunity Moved Table 12 to page 22 Added 3 Device Operation on page 22 Added 3 4 Fail Safe Operating Mode on page 24 Moved Typical Performance Characteristics to page 25 Deleted RF Radiated Emissions section Deleted RF Magnetic and Common Mode Transient Immunity section Updated MSL rating to MSL2A Revision 1 0 to Revision 1 1 Numerous text edits...

Page 37: ...Rev 1 1 37 Si8410 20 21 5 kV Si8422 23 2 5 5 kV NOTES ...

Page 38: ...included herein Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability...

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