Silicon Laboratories Si5340, Manual

Page: 6 / 48

S i 5 3 4 1 / 4 0
6 Preliminary Rev. 0.9
Table 3. Input Specifications
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Units
Differential or Single-Ended - AC Coupled (IN0/IN0, IN1/IN1, IN2/IN2, FB_IN/FB_IN)
Input Frequency Range f
IN_DIFF
10 — 750 MHz
Voltage Swing V
IN
f
in
< 400 MHz 100 — 1000 mVpp_se
600 MHz < f
in
<
800 MHz
225 — 1000 mVpp_se
f
in
> 800 MHz 375 — 1000 mVpp_se
Slew Rate
1, 2
SR 400 — — V/µs
Duty Cycle DC 40 — 60 %
Capacitance C
IN
— 2 — pF
LVCMOS - DC Coupled (IN0, IN1, IN2)
Input Frequency f
IN_CMOS
10 — 250 MHz
Input Voltage V
IL
-0.1 — 0.33 V
V
IH
0.80 — — V
Slew Rate
1, 2
SR 400 — — V/µs
Duty Cycle DC Clock Input 40 — 60 %
Minimum Pulse Width PW Pulse Input 1.6 — — ns
Input Resistance R
IN
— 8 — k
Ω
REFCLK (Applied to XA/XB)
REFCLK Frequency f
IN_REF
Frequency range
for best output
jitter performance
48 — 54 MHz
10 — 120 MHz
Input Voltage Swing V
IN
350 — 1600 mVpp_se
Slew rate
1, 2
SR Imposed for best
jitter performance
400 — — V/µs
Input Duty Cycle DC 40 — 60 %
Notes:
1. Imposed for jitter performance.
2. Rise and fall times can be estimated using the following simplified equation: tr/tf
80-20
= ((0.8 - 0.2) * V
IN_Vpp_se
) / SR.
3. V
DDIO
is determined by the IO_VDD_SEL bit. It is selectable as V
DDA
or V
DD
.