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Silicon Laboratories Si446 Series, Manual

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Silicon Laboratories Si446 Series Manual Download Page 43

AN625

Rev. 0.1

43

3.5.3. INT_CTL_MODEM_ENABLE

Summary: Modem interrupt enable property

Purpose:



Enables modem interrupt sources

Property: 0x0102

Default: 0x00

Fields:



INVALID_SYNC_EN - default:0 If set, Enables INVALID_SYNC interrupt.



RSSI_JUMP_EN - default:0 If set, Enables RSSI_JUMP interrupt.



RSSI_EN - default:0 If set, Enables RSSI interrupt.



INVALID_PREAMBLE_EN - default:0 If set, Enables INVALID_PREAMBLE interrupt.



PREAMBLE_DETECT_EN - default:0 If set, Enables PREAMBLE_DETECT interrupt.



SYNC_DETECT_EN - default:0 If set, Enables SYNC_DETECT interrupt.

Register View

3.5.4. INT_CTL_CHIP_ENABLE

Summary: Chip interrupt enable property 

Purpose:



Enables chip interrupt sources 

Property: 0x0103 

Default: 0x04 

Fields:



FIFO_UNDERFLOW_OVERFLOW_ERROR_EN - default:0 If set, Enables FIFO_UNDERFLOW_OVERFLOW_ERROR 

interrupt. 



STATE_CHANGE_EN - default:0 If set, Enables STATE_CHANGE interrupt. 



CMD_ERROR_EN - default:0 If set, Enables CMD_ERROR interrupt. 



CHIP_READY_EN - default:1 If set, Enables CHIP_READY interrupt. 



LOW_BATT_EN - default:0 If set, Enables LOW_BATT interrupt. 



WUT_EN - default:0 If set, Enables WUT interrupt. 

Register View 

INT_CTL_MODEM_ENABLE

7

6

5

4

3

2

1

0

0x0

INVALID_

SYNC_EN

RSSI_

JUMP_EN

RSSI_

EN

INVALID_

PREAMBLE_EN

PREAMBLE_

DETECT_EN

SYNC_

DETECT_EN

0x0

0

0

0

0

0

0

INT_CTL_CHIP_ENABLE

7

6

5

4

3

2

1

0

0x0

FIFO_UNDERFLOW_

OVERFLOW_ERROR_EN

STATE_

CHANGE_EN

CMD_

ERROR_EN

CHIP_

READY_EN

LOW_

BATT_EN

WUT_EN

0x0

0

0

0

1

0

0

Summary of Contents for Si446 Series

Page 1: ...12 GET_PROPERTY Retrieve a property s value 0x13 GPIO_PIN_CFG Configures the GPIO pins 0x14 GET_ADC_READING Retrieve the results of possible ADC conversions 0x15 FIFO_INFO Provides access to transmit and receive fifo counts and reset 0x16 GET_PACKET_INFO Returns information about the last packet received 0x17 IRCAL Calibrate Image Rejection Si4463 and Si4464 only 0x18 PROTOCOL_CFG Sets the chip up...

Page 2: ...er number 0x4001 FREQ_CONTROL_FRAC_2 0x08 Byte 2 of Frac N PLL fraction number 0x4002 FREQ_CONTROL_FRAC_1 0x00 Byte 1 of Frac N PLL fraction number 0x4003 FREQ_CONTROL_FRAC_0 0x00 Byte 0 of Frac N PLL fraction number 0x4004 FREQ_CONTROL_CHANNEL_STEP_SIZE_1 0x00 Byte 1 of channel step size 0x4005 FREQ_CONTROL_CHANNEL_STEP_SIZE_0 0x00 Byte 0 of channel step size 0x0000 GLOBAL_XO_TUNE 0x40 Configure ...

Page 3: ...ve the variable length information 0x120B PKT_TX_THRESHOLD 0x30 TX almost empty threshold 0x120C PKT_RX_THRESHOLD 0x30 RX almost full threshold 0x120D PKT_FIELD_1_LENGTH_12_8 0x00 Byte 1 of field length 0x120E PKT_FIELD_1_LENGTH_7_0 0x00 Byte 0 of field length 0x120F PKT_FIELD_1_CONFIG 0x00 Field 1 configuration bits 0x1210 PKT_FIELD_1_CRC_CONFIG 0x00 Field 1 CRC configuration bits 0x1211 PKT_FIEL...

Page 4: ...FIELD_3_LENGTH_12_8 0x00 Byte 1 of field length for RX 0x122A PKT_RX_FIELD_3_LENGTH_7_0 0x00 Byte 0 of field length for RX 0x122B PKT_RX_FIELD_3_CONFIG 0x00 Field 3 configuration bits for RX 0x122C PKT_RX_FIELD_3_CRC_CONFIG 0x00 Field 3 CRC configuration bits for RX 0x122D PKT_RX_FIELD_4_LENGTH_12_8 0x00 Byte 1 of field length for RX 0x122E PKT_RX_FIELD_4_LENGTH_7_0 0x00 Byte 0 of field length for...

Page 5: ...OL 0x01 RSSI control 0x204D MODEM_RSSI_CONTROL2 0x00 RSSI control 0x204E MODEM_RSSI_COMP 0x32 RSSI reading offset 0x2050 MODEM_RESERVED_20_50 0x00 0x2200 PA_MODE 0x10 PA operating mode and groups 0x2201 PA_PWR_LVL 0x7F PA Level Configuration 0x2202 PA_BIAS_CLKDUTY 0x00 PA Bias and TX clock duty cycle configu ration 0x2203 PA_TC 0x01 PA cascode ramping Configuration 0x3000 MATCH_VALUE_1 0x00 Match ...

Page 6: ...count adjustment for RX 0x5000 RX_HOP_CONTROL 0x04 RX hop control 0x5001 RX_HOP_TABLE_SIZE 0x01 Number of entries in the RX hop table 0x5002 RX_HOP_TABLE_ENTRY_0 0 No 1 entry in RX hopping table 0x500x RX_HOP_TABLE_ENTRY_xx 1 Entries 2 63 in RX hopping table 0x5041 RX_HOP_TABLE_ENTRY_64 2 No 3 entry in RX hopping table Common Properties Number Name Default Summary ...

Page 7: ... RAM but do not boot After CTS is set RAM may be patched via PATCH_ARGS and PATCH_DATA commands FUNC 5 0 Selects the boot function of the device 0 Boot Loader 1 Transceiver TCXO Select if TCXO is in use 0 XTAL is not TCXO 1 XTAL is TCXO XO_FREQ 31 0 Frequency of TCXO or external crystal oscillator in Hz The default is 30000000 30MHz Range 25000000 to 32000000 Response None POWER_UP Command 7 6 5 4...

Page 8: ...unction into RAM for execution or patching Command Stream Reply Stream Parameters FUNC 3 0 Selects the image to load 0 Boot Loader No image is loaded 1 Transceiver Response None PATCH_IMAGE Command 7 6 5 4 3 2 1 0 CMD 0x04 FLAGS 0000 FUNC 3 0 PATCH_IMAGE Reply 7 6 5 4 3 2 1 0 CMD_COMPLETE CMD_COMPLETE 7 0 ...

Page 9: ...NOP Summary No operation command Purpose Can be used to ensure communication with the device Command Stream Reply Stream Parameters None Response None NOP Command 7 6 5 4 3 2 1 0 CMD 0x00 NOP Reply 7 6 5 4 3 2 1 0 CMD_COMPLETE CMD_COMPLETE 7 0 ...

Page 10: ... CHIPREV 7 0 Chip Mask Revision PART 15 0 Part Number e g si4440 will return 0x4440 PBUILD 7 0 Part Build ID 15 0 ID CUSTOMER 7 0 Customer ID ROMID 7 0 ROM ID PART_INFO Command 7 6 5 4 3 2 1 0 CMD 0x01 PART_INFO Reply 7 6 5 4 3 2 1 0 CMD_COMPLETE CMD_COMPLETE 7 0 CHIPREV CHIPREV 7 0 PART PART 15 8 PART PART 7 0 PBUILD PBUILD 7 0 ID ID 15 8 ID ID 7 0 CUSTOMER CUSTOMER 7 0 ROMID ROMID 7 0 ...

Page 11: ...to 255 REVBRANCH 7 0 Branch revision number Range 0 to 255 REVINT 7 0 Internal revision number Range 0 to 255 PATCH 15 0 ID of applied patch This is also the last 2 bytes in the associated patch file csg 0x0000 No patch applied FUNC 7 0 Current functional mode 1 Tranceiver 2 Receive only 3 Transmit only FUNC_INFO Command 7 6 5 4 3 2 1 0 CMD 0x10 FUNC_INFO Reply 7 6 5 4 3 2 1 0 CMD_COMPLETE CTS 7 0...

Page 12: ... 0 Selects the property index to set The available properties are determined by the part number and the POWER_UP FUNC selection DATA0 7 0 Value of the property START_PROP DATA1 7 0 Value of the property START_PROP 1 don t care if NUM_PROPS 2 DATA2 7 0 Value of the property START_PROP 2 don t care if NUM_PROPS 3 DATA3 7 0 Value of the property START_PROP 3 don t care if NUM_PROPS 4 DATA4 7 0 Value ...

Page 13: ... 0 Value of the property START_PROP 7 don t care if NUM_PROPS 8 DATA8 7 0 Value of the property START_PROP 8 don t care if NUM_PROPS 9 DATA9 7 0 Value of the property START_PROP 9 don t care if NUM_PROPS 10 DATA10 7 0 Value of the property START_PROP 10 don t care if NUM_PROPS 11 DATA11 7 0 Value of the property START_PROP 11 don t care if NUM_PROPS 12 Response None ...

Page 14: ... 0 Selects the first property index to retrieve The available properties are determined by the part number and the POWER_UP FUNC selection GET_PROPERTY Command 7 6 5 4 3 2 1 0 CMD 0x12 GROUP GROUP 7 0 NUM_PROPS NUM_PROPS 7 0 START_PROP START_PROP 7 0 GET_PROPERTY Reply 7 6 5 4 3 2 1 0 CMD_COMPLETE CTS 7 0 DATA0 DATA0 7 0 DATA1 DATA1 7 0 DATA2 DATA2 7 0 DATA3 DATA3 7 0 DATA4 DATA4 7 0 DATA5 DATA5 7...

Page 15: ... care if NUM_PROPS 7 DATA7 7 0 Value of the property START_PROP 7 don t care if NUM_PROPS 8 DATA8 7 0 Value of the property START_PROP 8 don t care if NUM_PROPS 9 DATA9 7 0 Value of the property START_PROP 9 don t care if NUM_PROPS 10 DATA10 7 0 Value of the property START_PRO 10 don t care if NUM_PROPS 11 DATA11 7 0 Value of the property START_PROP 11 don t care if NUM_PROPS 12 DATA12 7 0 Value o...

Page 16: ...and complete high otherwise 10 High when command overlap occurs TODO What clears this GPIO_PIN_CFG Command 7 6 5 4 3 2 1 0 CMD 0x13 GPIO0 0 GPIO0_PULL_CTL GPIO0_MODE 5 0 GPIO1 0 GPIO1_PULL_CTL GPIO1_MODE 5 0 GPIO2 0 GPIO2_PULL_CTL GPIO2_MODE 5 0 GPIO3 0 GPIO3_PULL_CTL GPIO3_MODE 5 0 NIRQ 0 NIRQ_DRV_PULL NIRQ_MODE 5 0 SDO 0 SDO_PULL_CTL SDO_MODE 5 0 GEN_CONFIG 0 DRV_STRENGTH 1 0 00000 GPIO_PIN_CFG ...

Page 17: ...ifo is almost full 35 High while the tx fifo is almost empty 36 High while the battery voltage is low 37 High when RSSI above clear channel assesment threshold goes low on sync detect or exiting rx state 38 Toggles when hop occurs 39 Toggles when the hop table wraps GPIO1_PULL_CTL 0 Disable pullup Recommended setting if pin is driven 1 Enable pullup GPIO1_MODE 5 0 0 Do not modify the behavior of t...

Page 18: ...n 1 Input and output drivers disabled 2 CMOS output driven low 3 CMOS output driven high 4 CMOS input 5 32 kHz clock 6 30 MHz clock 7 Divided MCU clock 8 High when command complete low otherwise 9 Low when command complete high otherwise 10 High when command overlap occurs TODO What clears this 11 Serial data out 12 Pulses high on power on reset 13 Pulses high when calibration timer expires 14 Pul...

Page 19: ... 16 TX data CLK output to be used in conjuction with TX Data pin 17 RX data CLK output to be used in conjuction with RX Data pin 18 unused1 19 TX data 20 RX data 21 RX raw data 22 Antenna 1 Switch used for antenna diversity 23 Antenna 2 Switch used for antenna diversity 24 High when a valid preamble is detected Cleared when sync is received 25 High when an invalid preamble is detected TODO What cl...

Page 20: ... Active low interrupt signal SDO_PULL_CTL 0 Disable pullup Recommended setting if pin is driven 1 Enable pullup SDO_MODE 5 0 0 Do not modify the behavior of this pin 1 Input and output drivers disabled 2 CMOS output driven low 3 CMOS output driven high 4 CMOS input 5 32 kHz clock 7 Divided MCU clock 8 High when command complete low otherwise 11 Serial data out 12 Pulses high on power on reset 14 P...

Page 21: ...n wakeup timer expires 15 unused0 16 TX data CLK output to be used in conjuction with TX Data pin 17 RX data CLK output to be used in conjuction with RX Data pin 18 unused1 19 TX data 20 RX data 21 RX raw data 22 Antenna 1 Switch used for antenna diversity 23 Antenna 2 Switch used for antenna diversity 24 High when a valid preamble is detected Cleared when sync is received 25 High when an invalid ...

Page 22: ...en a valid preamble is detected Cleared when sync is received 25 High when an invalid preamble is detected TODO What clears this 26 High when a sync word is detected TODO What clears this 27 High when RSSI above clear channel assesment threshold low when below threshold 32 High while in the transmit state 33 High while in the receive state 34 High while the rx fifo is almost full 35 High while the...

Page 23: ...ile in the receive state 34 High while the rx fifo is almost full 35 High while the tx fifo is almost empty 36 High while the battery voltage is low 37 High when RSSI above clear channel assesment threshold goes low on sync detect or exiting rx state 38 Toggles when hop occurs 39 Toggles when the hop table wraps GPIO3STATE 0 Pin was read back as a 0 1 Pin was read back as a 1 GPIO3r 5 0 0 Do not m...

Page 24: ...s a 1 NIRQr 5 0 0 Do not modify the behavior of this pin 1 Input and output drivers disabled 2 CMOS output driven low 3 CMOS output driven high 4 CMOS input 7 Divided MCU clock 8 High when command complete low otherwise 11 Serial data out 12 Pulses high on power on reset 15 unused0 16 TX data CLK output to be used in conjuction with TX Data pin 17 RX data CLK output to be used in conjuction with R...

Page 25: ... Switch used for antenna diversity 23 Antenna 2 Switch used for antenna diversity 24 High when a valid preamble is detected Cleared when sync is received 25 High when an invalid preamble is detected TODO What clears this 26 High when a sync word is detected TODO What clears this 27 High when RSSI above clear channel assesment threshold low when below threshold DRV_STRENGTH 6 5 0 GPIOs configured a...

Page 26: ...ts in ADC_GPIO Vgpio 3 GPIO_ADC 1280 ADC_GPIO_PIN 1 0 Select GPIOx pin The pin must be set as input 0 Measure votage of GPIO0 1 Measure votage of GPIO1 2 Measure votage of GPIO2 3 Measure votage of GPIO3 Response GPIO_ADC 15 0 ADC value of voltage on GPIO BATTERY_ADC 15 0 ADC value of battery voltage TEMP_ADC 15 0 ADC value of temperature sensor voltage of the chip in degrees kelvin TEMP_SLOPE 7 0...

Page 27: ...out the last packet received Purpose This command is used to retrieve the length field extracted from the packet when using variable length packets Command Stream Reply Stream Parameters None Response LENGTH_15_8 7 0 Most significant byte of the extracted length LENGTH_7_0 7 0 Least significant byte of the extracted length FIFO_INFO Command 7 6 5 4 3 2 1 0 CMD 0x15 FIFO 000000 RX TX FIFO_INFO Repl...

Page 28: ... 0 is usedn to skip course stepping RSSI_FINE_AVG 5 4 How many measurements 2 avg per RSSI measurement while fine stepping 0 1 measurements 1 2 measurements 2 4 measurements 3 8 measurements RSSI_COURSE_AVG 1 0 How many measurements 2 avg per RSSI measurement while course stepping 0 1 measurements 1 2 measurements 2 4 measurements 3 8 measurements EN_HRMNIC_GEN Enable harmonic generator 0 Not enab...

Page 29: ...nd Stream Reply Stream Parameters PROTOCOL 7 0 TODO 0 Packet format is generic no dynamic reprogramming of packet handler properties 1 Packet format is IEEE802 15 4g compliance The following properties are overriden PKT_CRC_CONFIG CRC_ENDIAN BIT_ORDER in PKT_CONFG1 for TX and RX PKT_FIELD_X_CRC_CONFIG for RX Other applicable properties in the packet handler group still need to be programmed Field ...

Page 30: ...D_CL R STATE_ CHANGE _ PEND_ CLR CMD_ ERROR _PEND _ CLR CHIP_READY _PEND_CLR LOW_BATT _PEND_CL R WUT_PEND_ CLR GET_INT_ STATUS Reply 7 6 5 4 3 2 1 0 CMD_ COMPLETE CTS 7 0 INT_PEND XXXXX CHIP_INT_ STATUS_ PEND MODEM_ INT_STATUS_ PEND PH_INT_ STATUS_ PEND INT_STATUS XXXXX CHIP_INT_ STATUS MODEM_INT_ STATUS PH_INT_ STATUS PH_PEND FILTER_ MATCH_ PEND FILTER_ MISS_ PEND PACKET_ SENT_PEND PACKET_ RX_PEN...

Page 31: ...r pending STATE_CHANGE interrupt If set leave interrupt pending CMD_ERROR_PEND_CLR If clear Clear pending CMD_ERROR interrupt If set leave interrupt pending CHIP_READY_PEND_CLR If clear Clear pending CHIP_READY interrupt If set leave interrupt pending LOW_BATT_PEND_CLR If clear Clear pending LOW_BATT interrupt If set leave interrupt pending WUT_PEND_CLR If clear Clear pending WUT interrupt If set ...

Page 32: ...ove MODEM_RSSI_THRESH INVALID_PREAMBLE If set invalid preamble has been detected PREAMBLE_DETECT If set preamble has been detected SYNC_DETECT If set sync has been detected FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND If set FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt is pending STATE_CHANGE_PEND If set STATE_CHANGE interrupt is pending CMD_ERROR_PEND If set CMD_ERROR interrupt is pending CHIP_READY_PEND If set...

Page 33: ...ding RX_FIFO_ALMOST_FULL_PEND If set RX_FIFO_ALMOST_FULL interrupt is pending FILTER_MATCH If set incoming packet matched filter FILTER_MISS If set incoming packet was discarded because filter did not match PACKET_SENT If set Packet Sent PACKET_RX If set Packet Received CRC32_ERROR If set CRC 32 error TX_FIFO_ALMOST_EMPTY If set TX fifo is below watermark RX_FIFO_ALMOST_FULL If set RX fifo is abov...

Page 34: ...cted PREAMBLE_DETECT If set preamble has been detected SYNC_DETECT If set sync has been detected CURR_RSSI 7 0 Current RSSI reading from the modem LATCH_RSSI 7 0 Latched RSSI reading from the modem as configured by MODEM_RSSI_CONTROL Reset to 0 at the start of every RX ANT1_RSSI 7 0 RSSI of ANT1 while antenna diversity Latched during preamble evaluation and avaliable for reading after sync detecti...

Page 35: ...set a state change has occured CMD_ERROR If set command error has occured CHIP_READY If set chip is ready to accept commands LOW_BATT If set low battery has been detected WUT If set wakeup timer has expired CMD_ERR_STATUS 7 0 Last command error cause Only valid if CMD_ERROR status bit is set 0x00 No error 0x10 Bad command issued 0x11 Argment s in issued command were invalid 0x12 Command was issued...

Page 36: ...e 3 Ready state 4 Another enumeration for Ready state 5 Tune state for TX 6 Tune state for RX 7 TX state 8 RX state RETRANSMIT 0 Send data that has been written to fifo If fifo is empty a fifo underflow interrupt will occur 1 Send last packet again If this option is used ensure that no new data is written to the fifo START 1 0 0 Start TX immediately 1 Start TX when wake up timer expires TX_LEN 15 ...

Page 37: ... immediately 1 Start RX when wake up timer expires RX_LEN 15 0 If this field is nonzero the packet will be received using only field 1 with no packet handler features eg crc whitening If this field is zero the configuration of the packet handler fields is used RXTIMEOUT_STATE 3 0 If preamble detection times out RX will transition to RXTIMEOUT_STATE See PREAMBLE_CONFIG_STD_2 for details regarding h...

Page 38: ... change 1 Sleep state 2 Spi Active state 3 Ready state 4 Another enumeration for Ready state 5 Tune state for TX 6 Tune state for RX 7 TX state 8 RX state RXINVALID_STATE 3 0 If CRC checking is enabled in case of CRC error RX will transition to RXINVALID_STATE 0 No change 1 Sleep state 2 Spi Active state 3 Ready state 4 Another enumeration for Ready state 5 Tune state for TX 6 Tune state for RX 7 ...

Page 39: ... Sleep state 2 Spi Active state 3 Ready state 4 Another enumeration for Ready state 5 Tune state for TX 6 Tune state for RX 7 TX state 8 RX state CURRENT_CHANNEL 7 0 POST_TX_STATE 2 0 1 2 3 4 POST_RX_STATE 2 0 1 2 3 4 REQUEST_DEVICE_STATE Command 7 6 5 4 3 2 1 0 CMD 0x33 REQUEST_DEVICE_STATE Reply 7 6 5 4 3 2 1 0 CMD_COMPLETE CTS 7 0 CURR_STATE XXXX MAIN_STATE 3 0 CURRENT_CHANNEL CURRENT_CHANNEL 7...

Page 40: ...te transitions Command Stream Reply Stream Parameters NEW_STATE 3 0 State to go to immediately 0 No change 1 Sleep state 2 Spi Active state 3 Ready state 4 Another enumeration for Ready state 5 Tune state for TX 6 Tune state for RX 7 TX state 8 RX state Response None CHANGE_STATE Command 7 6 5 4 3 2 1 0 CMD 0x34 CHANGE_STATE Reply 7 6 5 4 3 2 1 0 CMD_COMPLETE CTS 7 0 ...

Page 41: ...d offline and stored in the host Command Stream Reply Stream Parameters INTE 7 0 INTE register value FRAC2 7 0 FRAC2 register value FRAC1 7 0 FRAC1 register value FRAC0 7 0 FRAC0 register value VCO_CNT0 7 0 VCO_CNT0 register value Response None RX_HOP Command 7 6 5 4 3 2 1 0 CMD 0x36 INTE INTE 7 0 FRAC2 FRAC2 7 0 FRAC1 FRAC1 7 0 FRAC0 FRAC0 7 0 VCO_CNT1 00000000 VCO_CNT0 VCO_CNT0 7 0 RX_HOP Reply ...

Page 42: ...0x00 Fields FILTER_MATCH_EN default 0 If set Enables FILTER_MATCH interrupt FILTER_MISS_EN default 0 If set Enables FILTER_MISS interrupt PACKET_SENT_EN default 0 If set Enables PACKET_SENT interrupt PACKET_RX_EN default 0 If set Enables PACKET_RX interrupt CRC32_ERROR_EN default 0 If set Enables CRC32_ERROR interrupt TX_FIFO_ALMOST_EMPTY_EN default 0 If set Enables TX_FIFO_ALMOST_EMPTY interrupt ...

Page 43: ... enable property Purpose Enables chip interrupt sources Property 0x0103 Default 0x04 Fields FIFO_UNDERFLOW_OVERFLOW_ERROR_EN default 0 If set Enables FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt STATE_CHANGE_EN default 0 If set Enables STATE_CHANGE interrupt CMD_ERROR_EN default 0 If set Enables CMD_ERROR interrupt CHIP_READY_EN default 1 If set Enables CHIP_READY interrupt LOW_BATT_EN default 0 If set...

Page 44: ..._A_MODE 7 0 default 0x01 0 Disabled Will always read back 0 1 Global status 2 Global interrupt pending 3 Packet Handler status 4 Packet Handler interrupt pending 5 Modem status 6 Modem interrupt pending 7 Chip status 8 Chip status interrupt pending 9 Current state 10 Latched RSSI value as defined in MODEM_RSSI_CONTROL LATCH Register View FRR_CTL_A_MODE 7 6 5 4 3 2 1 0 FRR_A_MODE 7 0 0x01 ...

Page 45: ..._B_MODE 7 0 default 0x02 0 Disabled Will always read back 0 1 Global status 2 Global interrupt pending 3 Packet Handler status 4 Packet Handler interrupt pending 5 Modem status 6 Modem interrupt pending 7 Chip status 8 Chip status interrupt pending 9 Current state 10 Latched RSSI value as defined in MODEM_RSSI_CONTROL LATCH Register View FRR_CTL_B_MODE 7 6 5 4 3 2 1 0 FRR_B_MODE 7 0 0x02 ...

Page 46: ..._C_MODE 7 0 default 0x09 0 Disabled Will always read back 0 1 Global status 2 Global interrupt pending 3 Packet Handler status 4 Packet Handler interrupt pending 5 Modem status 6 Modem interrupt pending 7 Chip status 8 Chip status interrupt pending 9 Current state 10 Latched RSSI value as defined in MODEM_RSSI_CONTROL LATCH Register View FRR_CTL_C_MODE 7 6 5 4 3 2 1 0 FRR_C_MODE 7 0 0x09 ...

Page 47: ..._A_MODE 7 0 default 0x00 0 Disabled Will always read back 0 1 Global status 2 Global interrupt pending 3 Packet Handler status 4 Packet Handler interrupt pending 5 Modem status 6 Modem interrupt pending 7 Chip status 8 Chip status interrupt pending 9 Current state 10 Latched RSSI value as defined in MODEM_RSSI_CONTROL LATCH Register View FRR_CTL_D_MODE 7 6 5 4 3 2 1 0 FRR_A_MODE 7 0 0x00 ...

Page 48: ...s are always sent bit 0 first Range 0 0xff Register View 3 5 10 SYNC_BITS_23_16 Summary Byte 2 of sync word Purpose Sync bytes are always sent bit 0 first Property 0x1102 Default 0xD4 Fields BITS_23_16 7 0 default 0xD4 Sync bytes are always sent bit 0 first Range 0 0xff Register View SYNC_BITS_31_24 7 6 5 4 3 2 1 0 BITS_31_24 7 0 0x2D SYNC_BITS_23_16 7 6 5 4 3 2 1 0 BITS_23_16 7 0 0xD4 ...

Page 49: ...IRECT_MODE_GPIO 1 0 default 0x0 0 TX direct mode uses gpio0 as data source applies to TX only 1 TX direct mode uses gpio1 as data source applies to TX only 2 TX direct mode uses gpio2 as data source applies to TX only 3 TX direct mode uses gpio3 as data source applies to TX only MOD_SOURCE 1 0 default 0x0 0 Modulation source is packet handler fifo 1 Modulation source is direct mode pin 2 Modulatio...

Page 50: ...te 6 0 default 0x3C Range 0 127 Register View 3 5 13 FREQ_CONTROL_FRAC_2 Summary Byte 2 of Frac N PLL fraction number Purpose Fractional N PLL fraction number defined by the modem calculator See data sheet for frequency equation for manual calculation Property 0x4001 Default 0x08 Fields frac_2 2 0 default 0x0 Range 0 7 Register View FREQ_CONTROL_INTE 7 6 5 4 3 2 1 0 0 INTE 6 0 0 0x3C FREQ_CONTROL_...

Page 51: ... Fields frac_1 7 0 default 0x00 Range 0 255 Register View 3 5 15 FREQ_CONTROL_FRAC_0 Summary Byte 0 of Frac N PLL fraction number Purpose Fractional N PLL fraction number defined by the modem calculator See datasheet for frequency equation for manual calculation Property 0x4003 Default 0x00 Fields frac_0 7 0 default 0x00 Range 0 255 Register View FREQ_CONTROL_FRAC_1 7 6 5 4 3 2 1 0 FRAC_1 7 0 0x00...

Page 52: ... 0x00 Range 0 255 Register View 3 5 17 FREQ_CONTROL_CHANNEL_STEP_SIZE_0 Summary Byte 0 of channel step size Purpose Channel frequency step size used when using EZ frequency programming EZ frequency programming is defined by base frequency inte frac channel number x step size Property 0x4005 Default 0x00 Fields channel_step_size_0 7 0 default 0x00 Range 0 255 Register View FREQ_CONTROL_CHANNEL_STEP...

Page 53: ...IDED_CLK_EN default 0 0 Divided clock output is disabled 1 Divided clock output is enabled DIVIDED_CLK_SEL 2 0 default 0x0 0 Clock output is system clock divided by 1 1 Clock output is system clock divided by 2 2 Clock output is system clock divided by 3 3 Clock output is system clock divided by 7 5 4 Clock output is system clock divided by 10 5 Clock output is system clock divided by 15 6 Clock o...

Page 54: ...t affect entire chip If PROTOCOL is specified the chip is placed into protocol aware state Property 0x0003 Default 0 Fields PROTOCOL 2 0 default 0x0 0x0 Packet format is generic no dynamic reprogramming of packet handler properties 0x1 Packet format is IEEE802 15 4g compliance POWER_MODE default 0 0 High performance mode for RX and TX RX current 13 mA 1 Low power mode for RX and TX RX current 10 m...

Page 55: ...ed on every 2 s 2 If the CAL function is enabled the chip will be powered on every 4 s 3 If the CAL function is enabled the chip will be powered on every 8 s 4 If the CAL function is enabled the chip will be powered on every 16 s 5 If the CAL function is enabled the chip will be powered on every 32 s 6 If the CAL function is enabled the chip will be powered on every 64 s 7 If the CAL function is e...

Page 56: ...elds WUT_M_15_8 7 0 default 0x00 Range 0 255 Register View 3 5 24 GLOBAL_WUT_M_7_0 Summary Configure WUT_M_7_0 Purpose Sets HW WUT_M lower byte Property 0x0006 Default 0x01 Fields WUT_M_7_0 7 0 default 0x01 Range 1 255 Register View GLOBAL_WUT_M_15_8 7 6 5 4 3 2 1 0 WUT_M_15_8 7 0 0x00 GLOBAL_WUT_M_7_0 7 6 5 4 3 2 1 0 WUT_M_7_0 7 0 0x01 ...

Page 57: ...WUT 1 Go to Sleep state after WUT WUT_R 4 0 default 0x00 Range 0 20 Register View 3 5 26 GLOBAL_WUT_LDC Summary Configure WUT_LDC Purpose Sets firmware internal WUT_LDC Property 0x0008 Default 0x00 Fields WUT_LDC 7 0 default 0x00 Range 0 255 Register View GLOBAL_WUT_R 7 6 5 4 3 2 1 0 0x0 WUT_SLEEP WUT_R 4 0 0x0 0 0x00 GLOBAL_WUT_LDC 7 6 5 4 3 2 1 0 WUT_LDC 7 0 0x00 ...

Page 58: ...1 Summary Standard preamble configuration Purpose Note This field only applies to standard preambles Property 0x1001 Default 0x14 Fields SKIP_SYNC_TIMEOUT default 0 0x1 In standard packet mode if set the system will ignore the syncword search timeout reset RX_THRESH 6 0 default 0x14 Number of preamble bits that must be valid to detect a valid preamble Zero is a valid value in this field means that...

Page 59: ...ry Standard preamble configuration Purpose Note This field only applies to standard preambles Property 0x1003 Default 0x0F Fields RX_PREAMBLE_TIMEOUT_EXTEND 3 0 default 0x0 This is only used for a long preamble timeout more than 15 nibbles If this field is non zero then PREAMBLE_TIMEOUT is RX_PREAMBLE_TIMEOUT_EXTEND by 15 nibbles up to 225 nibbles Range 0 15 RX_PREAMBLE_TIMEOUT 3 0 default 0xF Num...

Page 60: ...1 If the preamble pattern is 1010 the post Manchester transmitted bits will be 01100110 0x1 When Manchester is enabled if preamble pattern is 0101 the pre Manchester pattern will be 1111 the post Manchester transmitted bits will be 01010101 If the preamble pattern is 1010 the pre Manchester pattern will be 0000 the post Manchester transmitted bits will be 10101010 MAN_ENABLE default 0 0x0 Preamble...

Page 61: ...on standard preamble Range 0 0xff Register View 3 5 33 PREAMBLE_PATTERN_23_16 Summary Preamble pattern Purpose Preambles always sent bits 0 31 timewise Preamble pattern to be transmitted or expected to be received Field is expressed in chips after Manchester encoding or before Manchester decoding To use this register PREAM_CONFIG_STANDARD_PREAM should be set to 0 use non standard preamble Property...

Page 62: ...se non standard preamble Range 0 0xff Register View 3 5 35 PREAMBLE_PATTERN_7_0 Summary Preamble pattern Purpose Preambles always sent bits 0 31 timewise Preamble pattern to be transmitted or expected to be received Field is expressed in chips after Manchester encoding or before Manchester decoding To use this register PREAM_CONFIG_STANDARD_PREAM should be set to 0 use non standard preamble Proper...

Page 63: ...modulated MANCH default 0 0x0 Sync word is not manchester encoded 0x1 Sync word is manchester encoded LENGTH 1 0 default 0x1 0x0 Sync word is 8 bits sync byte 3 is used 0x1 Sync word is 16 bits sync bytes 2 and 3 are used 0x2 Sync word is 24 bits sync bytes 1 2 and 3 are used 0x3 Sync word is 32 bits sync bytes 0 1 2 and 3 are used Register View 3 5 37 SYNC_BITS_15_8 Summary Byte 1 of sync word Pu...

Page 64: ... 0 0 Use all 0s for the CRC Seed 1 Use all 1s for the CRC Seed CRC_POLYNOMIAL 3 0 default 0x0 0 No CRC 1 ITU T CRC8 X8 X2 X 1 2 IEC 16 X16 X14 X12 X11 X9 X8 X7 X4 X 1 3 Baicheva 16 X16 X15 X12 X7 X6 X4 X3 1 4 CRC 16 IBM X16 X15 X2 1 5 CCIT 16 X16 X12 X5 1 6 Koopman X32 X30 X29 X28 X26 X20 X19 X17 X16 X15 X11 X10 X7 X6 X4 X2 X 1 7 IEEE 802 3 X32 X26 X23 X22 X16 X12 X11 X10 X8 X7 X5 X4 X2 X 1 8 Cast...

Page 65: ...eceive chain enabled after packet received MANCH_POL default 0 0x0 0 is encoded decoded to from 01 Manchester pattern 0x1 0 is encoded decoded to from 10 Manchester pattern CRC_INVERT default 0 0x0 Leave each CRC bit intact 0x1 Invert each CRC bit before transmit Invert received CRC before comparison Data in fifo remains untouched CRC_ENDIAN default 0 0x0 CRC low bytes are received transmitted fir...

Page 66: ...IELD 2 0 default 0x0 Selects field number that will vary in length A value of 0 in this field specifies fixed packet length mode Field 2 to 5 can be designated as variable length field Register View 3 5 42 PKT_LEN_FIELD_SOURCE Summary Field number containing the embedded length field Purpose This property is used in variable packet mode defining where the length field is in the packet The length f...

Page 67: ...ted from the length field in the packet The result is used to set the length of the selected destination field that varies in length It is assumed the length field embedded in the packet includes the length field itself LEN_ADJUST can be set to 0xFF for 1byte length field or 0xFE for 2 byte length field if the length field is not inclusive LEN_ADJUST is a signed char Range 128 to 127 Register View...

Page 68: ...w 3 5 46 PKT_FIELD_1_LENGTH_12_8 Summary Byte 1 of field length Purpose This property specifices the length of this field in bytes A value of zero in this property means that the field is not used If the field is programmed as a variable length field this property sets the maximum length of the field Used along with byte 0 property Property 0x120D Default 0x00 Fields FIELD_1_LENGTH_12_8 4 0 defaul...

Page 69: ...Purpose Field 1 configuration bits common to TX and RX Property 0x120F Default 0x00 Fields 4FSK default 0 0x1 Enable 4fsk on this field PN_START default 0 0x1 Load PN 9 engine with seed value at the start of this field WHITEN default 0 0x1 Enable whitening on this field MANCH default 0 0x1 Enable manchester encoding on this field Register View PKT_FIELD_1_LENGTH_7_0 7 6 5 4 3 2 1 0 FIELD_1_LENGTH_...

Page 70: ...C over this field Register View 3 5 50 PKT_FIELD_2_LENGTH_12_8 Summary Byte 1 of field length Purpose This property specifices the length of this field in bytes A value of zero in this property means that the field is not used If the field is programmed as a variable length field this property sets the maximum length of the field Used along with byte 0 property Property 0x1211 Default 0x00 Fields ...

Page 71: ...Field 2 configuration bits Purpose Field 2 configuration bits common to TX and RX Property 0x1213 Default 0x00 Fields 4FSK default 0 0x1 Enable 4fsk on this field RESERVED default 0 Reserved WHITEN default 0 0x1 Enable whitening on this field MANCH default 0 0x1 Enable manchester encoding on this field Register View PKT_FIELD_2_LENGTH_7_0 7 6 5 4 3 2 1 0 FIELD_2_LENGTH_7_0 7 0 0x00 PKT_FIELD_2_CON...

Page 72: ...5 54 PKT_FIELD_3_LENGTH_12_8 Summary Byte 1 of field length Purpose This property specifices the length of this field in bytes A value of zero in this property means that the field is not used If the field is programmed as a variable length field this property sets the maximum length of the field Used along with byte 0 property Property 0x1215 Default 0x00 Fields FIELD_3_LENGTH_12_8 4 0 default 0x...

Page 73: ...Field 3 configuration bits Purpose Field 3 configuration bits common to TX and RX Property 0x1217 Default 0x00 Fields 4FSK default 0 0x1 Enable 4fsk on this field RESERVED default 0 Reserved WHITEN default 0 0x1 Enable whitening on this field MANCH default 0 0x1 Enable manchester encoding on this field Register View PKT_FIELD_3_LENGTH_7_0 7 6 5 4 3 2 1 0 FIELD_3_LENGTH_7_0 7 0 0x00 PKT_FIELD_3_CON...

Page 74: ...5 58 PKT_FIELD_4_LENGTH_12_8 Summary Byte 1 of field length Purpose This property specifices the length of this field in bytes A value of zero in this property means that the field is not used If the field is programmed as a variable length field this property sets the maximum length of the field Used along with byte 0 property Property 0x1219 Default 0x00 Fields FIELD_4_LENGTH_12_8 4 0 default 0x...

Page 75: ...Field 4 configuration bits Purpose Field 4 configuration bits common to TX and RX Property 0x121B Default 0x00 Fields 4FSK default 0 0x1 Enable 4fsk on this field RESERVED default 0 Reserved WHITEN default 0 0x1 Enable whitening on this field MANCH default 0 0x1 Enable manchester encoding on this field Register View PKT_FIELD_4_LENGTH_7_0 7 6 5 4 3 2 1 0 FIELD_4_LENGTH_7_0 7 0 0x00 PKT_FIELD_4_CON...

Page 76: ...5 62 PKT_FIELD_5_LENGTH_12_8 Summary Byte 1 of field length Purpose This property specifices the length of this field in bytes A value of zero in this property means that the field is not used If the field is programmed as a variable length field this property sets the maximum length of the field Used along with byte 0 property Property 0x121D Default 0x00 Fields FIELD_5_LENGTH_12_8 4 0 default 0x...

Page 77: ...Field 5 configuration bits Purpose Field 5 configuration bits common to TX and RX Property 0x121F Default 0x00 Fields 4FSK default 0 0x1 Enable 4fsk on this field RESERVED default 0 Reserved WHITEN default 0 0x1 Enable whitening on this field MANCH default 0 0x1 Enable manchester encoding on this field Register View PKT_FIELD_5_LENGTH_7_0 7 6 5 4 3 2 1 0 FIELD_5_LENGTH_7_0 7 0 0x00 PKT_FIELD_5_CON...

Page 78: ...RX_FIELD_1_LENGTH_12_8 Summary Byte 1 of field length for RX Purpose This property specifices the length of this field in bytes A value of zero in this property means that the field is not used If the field is programmed as a variable length field this property sets the maximum length of the field Used along with byte 0 property Property 0x1221 Default 0x00 Fields RX_FIELD_1_LENGTH_12_8 4 0 defaul...

Page 79: ... bits for RX Purpose Field 1 configuration bits for RX Property 0x1223 Default 0x00 Fields 4FSK default 0 0x1 Enable 4fsk on this field PN_START default 0 0x1 Load PN 9 engine with seed value at the start of this field WHITEN default 0 0x1 Enable whitening on this field MANCH default 0 0x1 Enable manchester encoding on this field Register View PKT_RX_FIELD_1_LENGTH_7_0 7 6 5 4 3 2 1 0 RX_FIELD_1_L...

Page 80: ...ENGTH_12_8 Summary Byte 1 of field length for RX Purpose This property specifices the length of this field in bytes A value of zero in this property means that the field is not used If the field is programmed as a variable length field this property sets the maximum length of the field Used along with byte 0 property Property 0x1225 Default 0x00 Fields RX_FIELD_2_LENGTH_12_8 4 0 default 0x00 0x0 B...

Page 81: ...ummary Field 2 configuration bits for RX Purpose Field 2 configuration bits for RX Property 0x1227 Default 0x00 Fields 4FSK default 0 0x1 Enable 4fsk on this field RESERVED default 0 Reserved WHITEN default 0 0x1 Enable whitening on this field MANCH default 0 0x1 Enable manchester encoding on this field Register View PKT_RX_FIELD_2_LENGTH_7_0 7 6 5 4 3 2 1 0 RX_FIELD_2_LENGTH_7_0 7 0 0x00 PKT_RX_F...

Page 82: ... length for RX Purpose This property specifices the length of this field in bytes A value of zero in this property means that the field is not used If the field is programmed as a variable length field this property sets the maximum length of the field Used along with byte 0 property Property 0x1229 Default 0x00 Fields RX_FIELD_3_LENGTH_12_8 4 0 default 0x00 0x0 Bit 8 to 12 of the field length Reg...

Page 83: ...ummary Field 3 configuration bits for RX Purpose Field 3 configuration bits for RX Property 0x122B Default 0x00 Fields 4FSK default 0 0x1 Enable 4fsk on this field RESERVED default 0 Reserved WHITEN default 0 0x1 Enable whitening on this field MANCH default 0 0x1 Enable manchester encoding on this field Register View PKT_RX_FIELD_3_LENGTH_7_0 7 6 5 4 3 2 1 0 RX_FIELD_3_LENGTH_7_0 7 0 0x00 PKT_RX_F...

Page 84: ... length for RX Purpose This property specifices the length of this field in bytes A value of zero in this property means that the field is not used If the field is programmed as a variable length field this property sets the maximum length of the field Used along with byte 0 property Property 0x122D Default 0x00 Fields RX_FIELD_4_LENGTH_12_8 4 0 default 0x00 0x0 Bit 8 to 12 of the field length Reg...

Page 85: ...ummary Field 4 configuration bits for RX Purpose Field 4 configuration bits for RX Property 0x122F Default 0x00 Fields 4FSK default 0 0x1 Enable 4fsk on this field RESERVED default 0 Reserved WHITEN default 0 0x1 Enable whitening on this field MANCH default 0 0x1 Enable manchester encoding on this field Register View PKT_RX_FIELD_4_LENGTH_7_0 7 6 5 4 3 2 1 0 RX_FIELD_4_LENGTH_7_0 7 0 0x00 PKT_RX_F...

Page 86: ... length for RX Purpose This property specifices the length of this field in bytes A value of zero in this property means that the field is not used If the field is programmed as a variable length field this property sets the maximum length of the field Used along with byte 0 property Property 0x1231 Default 0x00 Fields RX_FIELD_5_LENGTH_12_8 4 0 default 0x00 0x0 Bit 8 to 12 of the field length Reg...

Page 87: ...ummary Field 5 configuration bits for RX Purpose Field 5 configuration bits for RX Property 0x1233 Default 0x00 Fields 4FSK default 0 0x1 Enable 4fsk on this field RESERVED default 0 Reserved WHITEN default 0 0x1 Enable whitening on this field MANCH default 0 0x1 Enable manchester encoding on this field Register View PKT_RX_FIELD_5_LENGTH_7_0 7 6 5 4 3 2 1 0 RX_FIELD_5_LENGTH_7_0 7 0 0x00 PKT_RX_F...

Page 88: ...configuration bits Property 0x1234 Default 0x00 Fields RESERVED 1 0 default 0x0 Reserved CHECK_CRC32 default 0 0x1 Check CRC at the end of this field CRC32_ENABLE default 0 0x1 Enable CRC over this field Register View PKT_RX_FIELD_5_CRC_CONFIG 7 6 5 4 3 2 1 0 RESERVED 1 0 0x0 CHECK_CRC32 0 CRC32_ENABLE 0x0 0x0 0 0 0 ...

Page 89: ...rates in asynchronous mode applies to TX only GFSK is not supported TX_DIRECT_MODE_GPIO 1 0 default 0x0 0 TX direct mode uses gpio0 as data source applies to TX only 1 TX direct mode uses gpio1 as data source applies to TX only 2 TX direct mode uses gpio2 as data source applies to TX only 3 TX direct mode uses gpio3 as data source applies to TX only MOD_SOURCE 1 0 default 0x0 0 Modulation source i...

Page 90: ...nchester coding 1 Enable Manchester coding eninv_rxbit default 0 0 Do not invert RX data bits 1 Invert RX data bits eninv_txbit default 0 0 Do not invert TX data bits 1 Invert TX data bits eninv_fd default 0 If set frequency deviation s priority from negative to positive Register View MODEM_MAP_CONTROL 7 6 5 4 3 2 1 0 ENMANCH ENINV_RXBIT ENINV_TXBIT ENINV_FD 1 0 0 0 ...

Page 91: ... 0 0 DSM dithering is disabled 1 DSM dithering is enabled dsmdttp default 0 Dithering type 0 1 0 is added to DSM input LSB 1 1 1 is added to DSM input LSB dsm_rst default 0 0 DSM reset is not active 1 DSM will be in reset state until it is clear dsm_lsb default 1 If set DSM LSB input will be high all times dsm_order 1 0 default 0x3 DSM Mode 0 0 order with 0 output continuously 1 1st order on noise...

Page 92: ...Fields dr_23_16 7 0 default 0x0F Range 0 255 Register View 3 5 90 MODEM_DATA_RATE_1 Summary Byte 1 of TX data rate in bps bits per second Purpose Data rate unsigned 24 bit 100 kbps by default Property 0x2004 Default 0x42 Fields dr_15_8 7 0 default 0x42 Range 0 255 Register View MODEM_DATA_RATE_2 7 6 5 4 3 2 1 0 DR_23_16 7 0 0x0F MODEM_DATA_RATE_1 7 6 5 4 3 2 1 0 DR_15_8 7 0 0X42 ...

Page 93: ...fault 0x40 Range 0 255 Register View 3 5 92 MODEM_FREQ_DEV_2 Summary Byte 2 of TX frequency deviation a 17 bit unsigned number This only programs the MSB of TX frequency deviation Purpose Frequency deviation unsigned 17 bit Property 0x200A Default 0x00 Fields freqdev_16 default 0 Register View MODEM_DATA_RATE_0 7 6 5 4 3 2 1 0 dr_7_0 7 0 0x40 MODEM_FREQ_DEV_2 7 6 5 4 3 2 1 0 0x00 FREQDEV_16 0x00 0...

Page 94: ...freqdev_15_8 7 0 default 0x06 Range 0 255 Register View 3 5 94 MODEM_FREQ_DEV_0 Summary Byte 0 of frequency deviation Purpose Frequency deviation unsigned 17 bit Property 0x200C Default 0xD3 Fields freqdev_7_0 7 0 default 0xD3 Range 0 255 Register View MODEM_FREQ_DEV_1 7 6 5 4 3 2 1 0 freqdev_15_8 7 0 0x06 MODEM_FREQ_DEV_0 7 6 5 4 3 2 1 0 freqdev_7_0 7 0 0xD3 ...

Page 95: ...ds RESERVED_20_0D 7 0 default 0x00 Register View 3 5 96 MODEM_RESERVED_20_0E Summary Purpose Property 0x200E Default 0x00 Fields RESERVED_20_0E 7 0 default 0x00 Register View MODEM_RESERVED_20_0D 7 6 5 4 3 2 1 0 RESERVED_20_0D 7 0 0x00 MODEM_RESERVED_20_0E 7 6 5 4 3 2 1 0 RESERVED_20_0E 7 0 0x00 ...

Page 96: ...iv 2 0 default 0x0 The GPIO must be configured for antenna diversity for the algorithm to work properly 0 RX TX state GPIO Ant1 1 GPIO Ant2 0 Non RX TX State GPIO Ant1 0 GPIO Ant2 0 1 RX TX state GPIO Ant1 0 GPIO Ant2 1 Non RX TX State GPIO Ant1 0 GPIO Ant2 0 2 RX TX state GPIO Ant1 1 GPIO Ant2 0 Non RX TX State GPIO Ant1 1 GPIO Ant2 1 3 RX TX state GPIO Ant1 0 GPIO Ant2 1 Non RX TX State GPIO Ant...

Page 97: ...ld for clear channel assessment If RSSI value is above this threshold the CCA GPIO will be high and the RSSI interrupt will be generated Range 0 255 Register View 3 5 99 MODEM_RSSI_JUMP_THRESH Summary RSSI jumping detection threshold Purpose RSSI jumping detection threshold step in 1dB Property 0x204B Default 0x0C Fields rssijmpthd 6 0 default 0x0C RSSI jumping detection threshold Register View MO...

Page 98: ...RSSI jump as configured by MODEM_RSSI_CONTROL while receiving a packet Can be useful to detect interferring or secondary incoming packet Property 0x204D Default 0x00 Fields rssijmp_dwn default 0 If set enable RSSI jumping down detection rssijmp_up default 0 If set enable RSSI jumping up detection enrssijmp default 0 Enable RSSI jumping detection Once RSSI difference between 2Tb or 4Tb is above the...

Page 99: ...l adjust RSSI up Property 0x204E Default 0x32 Fields rssi_comp 6 0 default 0x32 RSSI reading offset Range 0 127 Register View 3 5 103 MODEM_RESERVED_20_50 Summary Purpose Property 0x2050 Default 0x00 Fields RESERVED_20_50 7 0 default 0x00 Register View MODEM_RSSI_COMP 7 6 5 4 3 2 1 0 0 RSSI_COMP 6 0 0 0x32 MODEM_RESERVED_20_50 7 6 5 4 3 2 1 0 RESERVED_20_50 7 0 0x00 ...

Page 100: ...erved 6 Set for Si4460 7 Reserved 8 Set for Si4461 PA_MODE 1 0 default 0x0 PA mode 0 Switch for Square Wave or Class E 1 Switch Current 13 dBm 2 Switched Current 10 dBm Register View 3 5 105 PA_PWR_LVL Summary PA Power Level Configuration Purpose Adjusts the TX power level in fine resolution Property 0x2201 Default 0x7F Fields DDAC 6 0 default 0x7F Range 0 127 Register View PA_MODE 7 6 5 4 3 2 1 0...

Page 101: ...ault 0x00 Factor to multiply the PA output current as a way to control the output power setting Range 0 63 Register View 3 5 107 PA_TC Summary PA Ramping Time Control Register Purpose Ramps the PA power in a controlled fashion to minimize spectral emmissions 0 represents 2us 31 represents 30us which is the longest ramping time Property 0x2203 Default 0x01 Fields TC 4 0 default 0x01 Range 0 31 Regi...

Page 102: ...t 0x00 Fields VALUE_1 7 0 default 0x00 Range 0 0xFF Register View 3 5 109 MATCH_MASK_1 Summary Match 1 mask Purpose Property 0x3001 Default 0x00 Fields MASK_1 7 0 default 0x00 Range 0 0xFF Register View MATCH_VALUE_1 7 6 5 4 3 2 1 0 VALUE_1 7 0 0x00 MATCH_MASK_1 7 6 5 4 3 2 1 0 MASK_1 7 0 0x00 ...

Page 103: ... match MATCH_EN default 0 Note This bit is quite different from other pattern match controlling 1 Enable packet match OFFSET 4 0 default 0x00 Pattern match 1 offset in byte after sync word Range 0 0x1F Register View 3 5 111 MATCH_VALUE_2 Summary Match 2 value Purpose Property 0x3003 Default 0x00 Fields VALUE_2 7 0 default 0x00 Range 0 0xFF Register View MATCH_CTRL_1 7 6 5 4 3 2 1 0 POLARITY MATCH_...

Page 104: ...tern 2 matches or not Property 0x3005 Default 0x00 Fields POLARITY default 0 0x00 True if packet matches 0x01 True if packet doesn t match LOGIC default 0 0x00 AND with previous MATCH field 0x01 OR with previous MATCH field OFFSET 4 0 default 0x00 Match 2 offset in byte after sync word Range 0 0x1F Register View MATCH_MASK_2 7 6 5 4 3 2 1 0 MASK_2 7 0 0x00 MATCH_CTRL_2 7 6 5 4 3 2 1 0 POLARITY LOG...

Page 105: ...t 0x00 Fields VALUE_3 7 0 default 0x00 Range 0 0xFF Register View 3 5 115 MATCH_MASK_3 Summary Match 3 mask Purpose Property 0x3007 Default 0x00 Fields MASK_3 7 0 default 0x00 Range 0 0xFF Register View MATCH_VALUE_3 7 6 5 4 3 2 1 0 VALUE_3 7 0 0x00 MATCH_MASK_3 7 6 5 4 3 2 1 0 MASK_3 7 0 0x00 ...

Page 106: ...OGIC default 0 0x00 AND with previous MATCH field 0x01 OR with previous MATCH field OFFSET 4 0 default 0x00 Match 3 offset in byte after sync word Range 0 0x1F Register View 3 5 117 MATCH_VALUE_4 Summary Match 4 value Purpose Property 0x3009 Default 0x00 Fields VALUE_4 7 0 default 0x00 Range 0 0xFF Register View MATCH_CTRL_3 7 6 5 4 3 2 1 0 POLARITY LOGIC 0 OFFSET 4 0 0 0 0 0x00 MATCH_VALUE_4 7 6 ...

Page 107: ...tern 4 matches or not Property 0x300B Default 0x00 Fields POLARITY default 0 0x00 True if packet matches 0x01 True if packet doesn t match LOGIC default 0 0x00 AND with previous MATCH field 0x01 OR with previous MATCH field OFFSET 4 0 default 0x00 Match 4 offset in byte after sync word Range 0 0x1F Register View MATCH_MASK_4 7 6 5 4 3 2 1 0 MASK_4 7 0 0x00 MATCH_CTRL_4 7 6 5 4 3 2 1 0 POLARITY LOG...

Page 108: ...ge 0 255 Register View 3 5 121 FREQ_CONTROL_VCOCNT_RX_ADJ Summary VCO target count adjustment for RX Purpose VCO target count adjustment for RX signed Property 0x4007 Default 0xFF Fields vcocnt_rx_adj 7 0 default 0xFF Range 128 to 127 Register View FREQ_CONTROL_W_SIZE 7 6 5 4 3 2 1 0 W_SIZE 7 0 0x20 FREQ_CONTROL_VCOCNT_RX_ADJ 7 6 5 4 3 2 1 0 VCOCNT_RX_ADJ 7 0 0XFF ...

Page 109: ...er timeout condition forces hop whichever occurs first Otherwise stay on channel 3 Hop if preamble timeout or invalid sync word 4 Hop on RSSI timeout preamble timeout or invalid sync word RSSI_TIMEOUT 3 0 default 0x4 Sets the RSSI time out expressed in nibbles Register View 3 5 123 RX_HOP_TABLE_SIZE Summary Number of entries in the RX hop table Purpose Number of entries in the RX hop table Propert...

Page 110: ...e 0 255 255 Hopping entry is invalid Register View 3 5 125 RX_HOP_TABLE_ENTRY_xx Summary No x entry in RX hopping table Purpose No 2 entry in RX hopping table Skip this entry if 0xFF Property 0x50xx Default 1 Fields CHANNEL_NUM 7 0 default 0x01 Range 0 255 255 Hopping entry is invalid Register View RX_HOP_TABLE_ENTRY_0 7 6 5 4 3 2 1 0 CHANNEL_NUM 7 0 0x00 RX_HOP_TABLE_ENTRY_xx 7 6 5 4 3 2 1 0 CHAN...

Page 111: ...AN625 Rev 0 1 111 NOTES ...

Page 112: ... Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of...

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