Rev. 0.4
Copyright © 2014 by Silicon Laboratories
AN685
A N 6 8 5
L
A Y O U T
D
E S I G N
G
U I D E
F O R
T H E
S i 4 4 5 5 / 4 3 5
X
R F I C
S
1. Introduction
This application note provides guidelines and design examples to help users design PCBs for the next generation
EZRadio® RF ICs, such as the Si4455/435x devices, using good design practices that allow for high quality RF
performance. The RF performance and the critical maximum peak voltage on the output pin strongly depends on
the PCB layout as well as the design of the matching networks. The matching principles are described in detail in
“AN693: Si4455 Low Power PA Matching”. Furthermore, these types of RF ICs are also applicable in the RF Stick
and RF pico board solutions where a PCB antenna is used, which also requires some considerations in the layout
design. For optimal performance, Silicon Labs recommends using the PCB layout design suggestions described in
the following sections.
2. Design Recommendations when Using Si4455/435x RF ICs
Extensive testing has been completed using reference designs provided by Silicon Labs. It is recommended that
designers use the reference designs “as-is” since they minimize de-tuning effects caused by parasitics and
generated by component placement and PCB routing.
When layouts as shown by the reference designs cannot be followed (as a result of PCB size and shape
limitations), then the following layout design rules are recommended.
The Si4455 transceiver RF chip uses Class-E TX matching network and a 4-element matching balun on the RX
side in Direct Tie configuration (where the TX and RX paths are connected together directly without any additional
RF switch). Meanwhile, the Si435x receiver RF chip uses only the 4-element matching balun.
