Si4010-C2
142
Rev. 1.0
SFR Address = 0xCA
SFR Address = 0xCB
SFR Definition 34.3. TMR2RL
Bit
7
6
5
4
3
2
1
0
Name
TMR2RL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
Name
Function
7:0
TMR2RL[7:0]
Timer 2 Capture/Reload Register Low Byte.
TMR2RL holds the low byte of the capture/reload value for Timer 2. LSB Byte. Two
halves are not double buffered. Write to each of the halves takes effect immedi-
ately. If the timer or respective half operates in capture mode this register holds the
capture value. If the timer or respective half operates in timer mode this register
holds the reload value.
SFR Definition 34.4. TMR2RH
Bit
7
6
5
4
3
2
1
0
Name
TMR2RH[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
Name
Function
7:0
TMR2RH[7:0]
Timer 2 Capture/Reload Register High Byte.
TMR2RH holds the high byte of the reload value for Timer 2.
