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RS9116 CC0 Connectivity Module Datasheet v1.0.10, December 2021

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application layer supports all profiles supported by BlueZ on Linux. It has a wireless coexistence manager to arbitrate
between protocols.

The RS9116 software package is available in two flavors

•

Hosted mode (n-

Link™):

Wi-Fi stack, Bluetooth stack and profiles, and all network stacks reside on the host

processor. Support for multiple Virtual Access Points available.

•

Embedded mode (WiSeConnect™):

Wi-Fi stack, TCP/IP stack, IP modules, Bluetooth stack and some profiles

reside in RS9116; Some of the Bluetooth profiles reside in the host processor

NOTE

: Please refer to the Software Manuals (TRM and PRM) in

RS9116 Document Library

for more details.

4.2.6.1

Hosted Mode (n-

Link™)

•

Available host interfaces: SDIO 2.0 and USB HS

•

Support for 20 MHz channel bandwidth

•

Application data throughput up to 50 Mbps (Hosted Mode) in 802.11n with 20 MHz bandwidth

•

Host drivers for Linux

•

Support for Client mode, Access point mode (Up to 16 clients), Concurrent Client and Access Point mode, and
Enterprise Security

•

Support for concurrent Wi-Fi, dual-mode Bluetooth 5

4.2.6.2

Embedded Mode (WiSeConnect™)

•

Available host interface: UART, SPI, and USB CDC

•

Support for Embedded Client mode, Access Point mode (Up to 8 clients), Concurrent Client and Access Point
mode, and Enterprise Security

•

Supports advanced security features: WPA/WPA2-Personal and Enterprise

•

Integrated TCP/IP stack, HTTP/HTTPS, SSL/TLS, MQTT

•

Bluetooth inbuilt stack support for L2CAP, RFCOMM, SDP, SPP, GAP

•

Bluetooth profile support for GAP, SDP, SPP, GATT, L2CAP, RFCOMM

•

Wireless firmware update and provisioning

•

Support for concurrent Wi-Fi, dual-mode Bluetooth 5

* For a detailed list of software features and available profiles, refer to the Software Reference Manuals or
contact Silicon Labs for availability.

4.2.7 Security

RS9116 supports multiple levels of security capabilities available for the development of IoT devices.

•

Accelerators: AES128/256 in Embedded Mode

•

WPA/WPA2-Personal, WPA/WPA2 Enterprise for Client

* For a detailed list of software features and available profiles, refer to the Software Reference Manuals or
contact Silicon Labs for availability.

4.2.8 Power Management

The RS9116 chipsets have an internal power management subsystem, including DC-DC converters and linear
regulators. This subsystem generates all the voltages required by the chipset to operate from a wide variety of input
sources.

•

LC DC-DC switching converter for RF and Digital blocks

Summary of Contents for RS9116

Page 1: ...processor with calibration memory RF transceiver high power amplifier balun and T R switch Dual external antenna diversity supported Power Consumption 2 4 GHz Wi Fi Standby Associated mode current 102 uA 1 second beacon interval Wi Fi 1 Mbps Listen current 14 mA Wi Fi LP chain Rx current 20 mA Deep sleep current 1 uA Standby current RAM retention 10 uA Operating Conditions Operating supply range 3...

Page 2: ...s Smart Watches Wristbands Fitness Monitors Smart Glasses etc Smart Home Smart Locks Motion Entrance Sensors Water Leak sensors Smart plugs switches LED lights Door bell cameras Washers Dryers Refrigerators Thermostats Consumer Security cameras Voice Assistants etc Other Consumer Applications Toys Anti theft tags Smart dispensers Weighing scales Blood pressure monitors Blood sugar monitors Portabl...

Page 3: ...nnectivity Module Datasheet v1 0 10 December 2021 silabs com Building a more connected world Rev 1 0 10 3 Page 1 4 Block Diagrams Figure 1 CC0 Module Block Diagram Figure 2 RS9116 Connectivity Hardware Block Diagram ...

Page 4: ...10 December 2021 silabs com Building a more connected world Rev 1 0 10 4 Page Figure 3 Hosted Software Architecture Figure 4 Embedded Software Architecture Customer can connect multiple hosts but only one host interface can be active after power on ...

Page 5: ...ransmitter Characteristics 41 3 5 2 WLAN 2 4 GHz Receiver Characteristics on High Performance HP RF Chain 43 3 5 3 WLAN 2 4 GHz Receiver Characteristics on Low Power LP RF Chain 44 3 5 4 Bluetooth Transmitter Characteristics on High Performance HP RF Chain 46 3 5 5 Bluetooth Transmitter Characteristics on Low Power LP 0 dBm RF Chain 48 3 5 6 Bluetooth Receiver Characteristics on High Performance H...

Page 6: ...RS9116 CC0 Module Certification and Ordering Information 82 7 1 Certification Information 82 7 2 Compliance and Certification 82 7 2 1 Federal Communication Commission Statement 82 7 2 2 Industry Canada ISED Statement 83 7 2 3 CE 84 7 2 4 TELEC 84 7 2 5 Qualified Antenna Types 84 7 2 6 Module Marking Information 85 7 3 Module Package 86 7 4 Ordering Information 86 8 RS9116 CC0 Module Documentation...

Page 7: ...PIO_48 GPIO_49 GPIO_46 NC ULP_GPIO_8 NC NC UART2_TX ULP_GPIO_6 PA2G_AVDD UULP_VBAT_GPIO_3 GPIO_12 GPIO_10 UART1_TX GPIO_6 ULP_GPIO_4 GND ULP_GPIO_7 JP2 JNC GND GND GND GND UULP_VBAT_GPIO_4 NC NC ULP_GPIO_10 JP0 JP1 NC GND GND GND GND GND GND POC_IN HOST_BYP_ULP_WAKEUP ULP_GPIO_5 TRST GND PA5G_AVDD VOUTLDOAFE GND RF_AVDD_BTTX GND GND GND GND ULP_GPIO_11 POC_OUT AVDD_1P2 GND AVDD_1P9_3P3 GND GND GND...

Page 8: ... per the Reference Schematics RESET_N K2 UULP_VBATT_1 Input NA Active low reset asynchronous reset signal POC_IN H1 UULP_VBATT_1 Input NA Power On Control Input This is an input to the chip It should be made high only after supplies are valid to ensure the IC is in safe state until valid power supply is available POC_OUT J2 UULP_VBATT_1 Ouput NA Power On Control Output This is internally generated...

Page 9: ...s have this as the I O supply ULP_IO_VDD Power B6 Input I O Supply for ULP GPIOs PA2G_AVDD Power E9 Input Power supply for the 2 4 GHz RF Power Amplifier PA5G_AVDD Power H7 N7 Input Power supply for the 5 GHz RF Power Amplifier RF_AVDD Power D10 Input Power supply for the 2 4 GHz RF and AFE Connect to VOUTBCKDC as per the Reference Schematics RF_AVDD_BTTX Power H10 Input Power supply for Bluetooth...

Page 10: ...following I2S_DOUT I2S interface output data PCM_DOUT PCM interface output data GPIO_7 D9 IO_VDD_1 Inout HighZ Default HighZ Sleep HighZ This pin can be configured by software to be any of the following I2S_CLK I2S interface clock USB_AVDD_3P3 Power B7 Input Power Supply for the USB interface USB_AVDD_1P1 Power A5 Input Power supply for the USB core GND Ground B1 B13 C4 D8 F2 F6 F10 F11 F12 F13 G8...

Page 11: ...n UART HighZ HighZ The UART interface is supported only in WiSeConnect GPIO_9 UART1_TX E13 IO_VDD_1 Inout HighZ Host Default Sleep UART UART1_TX UART Host interface serial output HighZ Non UART HighZ HighZ The UART interface is supported only in WiSeConnect GPIO_10 E12 IO_VDD_1 Inout HighZ Default HighZ Sleep HighZ This pin can be configured by software to be any of the following I2S_DIN I2S inter...

Page 12: ...e Request to Send if UART Host Interface flow control is enabled The UART interface is supported only in WiSeConnect GPIO_15 A12 IO_VDD_1 Inout HighZ Default HighZ Sleep HighZ This pin can be configured by software to be any of the following UART1_CTS UART interface Clear to Send if UART Host Interface flow control is enabled UART1_TRANSPARENT_MODE UART Host interface Transparent Mode Indication t...

Page 13: ...SDIO_CLK SDIO interface clock HighZ SPI SPI_CLK SPI Slave interface clock HighZ Non SDIO SPI HighZ HighZ The SPI interface is supported only in WiSeConnect SDIO_CMD SPI_CSN A10 SDIO_IO_VDD Inout HighZ Host Default Sleep SDIO SDIO_CMD SDIO interface CMD signal HighZ SPI SPI_CSN Active low Chip Select signal of SPI Slave interface HighZ Non SDIO SPI HighZ HighZ The SPI interface is supported only in...

Page 14: ...terface Master Out Slave In signal HighZ Non SDIO SPI HighZ HighZ The SPI interface is supported only in WiSeConnect SDIO_D1 SPI_MISO A9 SDIO_IO_VDD Inout HighZ Host Default Sleep SDIO SDIO_D1 SDIO interface Data1 signal HighZ SPI SPI_MISO SPI Slave interface Master In Slave Out signal HighZ Non SDIO SPI HighZ HighZ The SPI interface is supported only in WiSeConnect SDIO_D2 SPI_INTR B8 SDIO_IO_VDD...

Page 15: ...ignal to the Host HighZ Non SDIO SPI HighZ HighZ The SPI interface is supported only in WiSeConnect SDIO_D3 SPI_ERR_INT R USB_CDC_DIS A8 SDIO_IO_VDD Inout Pullup Host Default Sleep SDIO SDIO_D3 SDIO interface Data3 signal HighZ SPI SPI_ERR_I NTR SPI Bus Error Interrupt Signals HighZ USB USB_CDC_ DIS USB CDC Active High Disable Signal HighZ Non SDIO SPI HighZ HighZ The SPI interface is supported on...

Page 16: ..._VDD_1 Inout HighZ Default HighZ Sleep HighZ GPIO_49 D13 IO_VDD_1 Inout HighZ Default HighZ Sleep HighZ GPIO_50 B14 IO_VDD_1 Inout HighZ Default HighZ Sleep HighZ GPIO_51 C14 IO_VDD_1 Inout HighZ Default HighZ Sleep HighZ GPIO_52 C11 IO_VDD_1 Inout HighZ Default HighZ Sleep HighZ GPIO_53 D11 IO_VDD_1 Inout HighZ Default HighZ Sleep HighZ GPIO_54 B12 IO_VDD_1 Inout HighZ Default HighZ Sleep HighZ G...

Page 17: ...erface This pin is intended to act as WLAN_ACTIVE for wireless coexistence Please contact Silicon Labs to learn about availability of this feature ULP_GPIO_1 B2 ULP_IO_VDD Inout HighZ Default HighZ Sleep HighZ This pin can be configured by software to be any of the following BT_ACTIVE Active High signal from an external Bluetooth IC that it is transmitting Part of the 3 wire coexistence interface ...

Page 18: ...he UART interface is supported only in WiSeConnect ULP_GPIO_6 E6 ULP_IO_VDD Inout HighZ Default HighZ Sleep HighZ This pin can be configured by software to be any of the following WAKEUP_FROM_Dev Used as a wakeup indication to host from device BT_PRIORITY Active high signal from an external Bluetooth IC that indicates that the Bluetooth transmissions are a higher priority For Wake on Wireless it i...

Page 19: ...rnal LED LED0 functionality currently not available in WiSeConnect modules ULP_GPIO_9 UART2_TX E5 ULP_IO_VDD Inout HighZ Default UART2_TX Debug UART Interface serial output Sleep HighZ UART2_TX Debug UART interface serial output ULP_GPIO_10 G3 ULP_IO_VDD Inout HighZ Default HighZ Sleep HighZ This pin can be configured by software to be any of the following I2C_SCL I2C interface clock ULP_GPIO_11 J...

Page 20: ...eep mode UULP_VBAT_GPIO_2 HOST_BYP_ULP_WAK EUP H3 UULP_VBATT_1 Input HighZ Default HOST_BYP Sleep ULP_WAKEUP This signal has two functionalities one during the bootloading process and one after the bootloading During bootloading this signal is an active high input to indicate that the bootloader should bypass any inputs from the Host processor and continue to load the default firmware from Flash A...

Page 21: ...LP Sleep mode UULP_VBAT_GPIO_4 F14 UULP_VBATT_1 Inout HighZ Default HighZ Sleep HighZ This pin can be configured by software to be any of the following XTAL_32KHZ_IN This pin can be used to feed external clock from a host processor or from external crystal oscillator JP0 G4 IO_VDD_1 Input Pullup Default JP0 Sleep HighZ JP0 Reserved Connect to a test point for debug purposes JP1 G5 IO_VDD_1 Input P...

Page 22: ...te refers to the state of the device after initial boot loading and firmware loading is complete 2 Sleep state refers to the state of the device after entering Sleep state which is indicated by Active Low SLEEP_IND_FROM_DEV signal 3 Please refer to RS9116N Open Source Driver Technical Reference Manual for software programming information in hosted mode 4 Please refer to RS9116W SAPI Programming Re...

Page 23: ...0 23 Page 2 2 4 Miscellaneous Pins Pin Name Pin Number I O Supply Domain Direction Initial State Power up Active Reset Description TRST H5 IO_VDD_1 NA NA Test signal Connect to Ground NC A1 A2 A13 C1 C3 C7 C8 D2 E1 E3 E4 G1 G2 G6 G7 K13 K14 L8 L14 M7 M8 N3 N4 N6 N9 N10 NA NA NA No connect Table 4 Miscellaneous Pins ...

Page 24: ... SDIO I Os 0 5 3 63 V ULP_IO_VDD I O supplies for ULP GPIOs 0 5 3 63 V PA2G_AVDD Power supply for the 2 4 GHz RF Power Amplifier 0 5 3 63 V PA5G_AVDD Power supply for the 5 GHz RF Power Amplifier 0 5 3 63 V RF_AVDD Power supply for the 2 4 GHz RF and AFE 0 5 1 98 V RF_AVDD_BTTX Power supply for Bluetooth Transmit circuit 0 5 1 21 V RF_AVDD33 Power supply for the 5 GHz RF 0 5 3 63 V AVDD_1P9_3P3 Po...

Page 25: ...upply for the 2 4 GHz RF and AFE 1 3 1 35 1 8 V RF_AVDD_BTTX Power supply for Bluetooth Transmit circuit 1 0 1 1 1 2 V RF_AVDD33 Power supply for the 5 GHz RF 3 3 3 3 6 V AVDD_1P9_3P3 Power supply for the 5 GHz RF 1 9 3 3 3 6 V AVDD_1P2 Power supply for the 5 GHz RF 1 2V 1 05 1 1 1 2 V UULP_AVDD Power supply for the always on digital and ULP peripherals 0 95 1 0 1 21 V USB_AVDD_3P3 Power supply fo...

Page 26: ... The diagram below shows connections of various power supply voltages POC_IN and RESET_N These connections can be used when System PMU outside RS9116 can provide 1 4V supply and hence the internal Buck regulator in RS9116 can be disabled The 1 1V supply is still derived from LDO SoC internal to RS9116 POC_IN is controlled externally NOTE 1 Above shown is a typical connection diagram Some of the su...

Page 27: ...lar waveform can be ignored and the RESET_N timing can be considered after before external power supplies ramp up down 3 3 2 2 Power Up and Down Sequence with External POC_IN The diagram below shows connections of various power supply voltages POC_IN and RESET_N These connections can be used when System PMU cannot provide 1 4V or 1 1V supplies and the internal buck and LDO of RS9116 are used POC_I...

Page 28: ...ion is Not Recommended for New Design System cannot provide external 1 4V 1 1V supplies and the internal buck and LDO of RS9116 are used POC_IN is looped back from POC_OUT NOTE 1 Above shown is a typical connection diagram Check the Reference Schematics for connections of other power supplies 2 POC_OUT can be connected to POC_IN if the supply voltage is 3 3V only Else POC_IN has to be driven exter...

Page 29: ...ity is enabled it will be 1 by default immediately after power on The diagram below shows typical connections of EXT_PG_EN and UULP_VBATT pins Use one of the application connections shown above in conjunction to the below The main purpose of this connection diagram and waveform is to show the EXT_PG_EN connection and its waveform in relation to the others NOTE 1 Above shown is a typical connection...

Page 30: ...tation Hence the start and ramp up timing of other power supplies does not have any timing requirement 3 3 3 Hardware Resetting Sequence after Power On During power up of the RS9116 a power up sequence must be followed as per the requirements mentioned in the above section In some applications there is a need to reset the RS9116 for a second time or beyond after power up Follow the below timing di...

Page 31: ...RS9116 CC0 Connectivity Module Datasheet v1 0 10 December 2021 silabs com Building a more connected world Rev 1 0 10 31 Page ...

Page 32: ...B Parameter Conditions Min Typ Max Units Vcm DC DC level measured at receiver connector HS Mode LS FS Mode 0 05 0 8 0 5 2 5 V Crossover Voltages LS Mode FS Mode 1 3 1 3 2 2 V Power supply ripple noise Analog 3 3V 160 MHz 50 50 mV Table 9 USB 3 3 6 Pin Capacitances Symbol Parameter Min Typ Max Unit Cio Input output capacitance digital pins only 2 0 pF Table 10 Pin Capacitances 3 4 AC Characteristic...

Page 33: ...kHz RC oscillator calibrated to 200ppm 32 kHz XTAL Oscillator clock is important for Low power Audio Streaming operation A2DP Source There is no impact on sleep deep sleep power consumption with without 32 kHz XTAL oscillator clock 32 kHz XTAL sources Option 1 From Host MCU MPU LVCMOS rail to rail clock input on UULPGPIO Option 2 External Xtal oscillator providing LVCMOS rail to rail clock input o...

Page 34: ...rameter Parameter Description Min Typ Max Unit Tsdio SDIO_CLK 25 MHz Ts SDIO_DATA SDIO_CMD input setup time 4 ns Th SDIO_DATA SDIO_CMD input hold time 1 ns Tod SDIO_DATA SDIO_CMD clock to output delay 13 ns CL Output Load 5 10 pF Table 13 AC Characteristics SDIO 2 0 Slave Full Speed Mode Figure 7 Interface Timing Diagram for SDIO 2 0 Slave Full Speed Mode 3 4 2 2 High Speed Mode Parameter Paramete...

Page 35: ... 5 ns Tcst SPI CS to input setup time 4 5 Ts SPI_MOSI input setup time 1 33 ns Th SPI_MOSI input hold time 1 2 ns Tod SPI_MISO clock to output delay 8 75 ns CL Output Load 5 10 pF Table 15 AC Characteristics SPI Slave Low Speed Mode Figure 9 Interface Timing Diagram for SPI Slave Low Speed Mode 3 4 3 2 High Speed Mode Parameter Parameter Description Min Typ Max Unit Tspi SPI_CLK 25 80 MHz Tcs SPI_...

Page 36: ...tics SPI Slave High Speed Mode Figure 10 Interface Timing Diagram for SPI Slave High Speed Mode 3 4 3 3 Ultra High Speed Mode Parameter Parameter Description Min Typ Max Unit Tspi SPI_CLK 100 MHz Ts SPI_MOSI input setup time 1 33 ns Th SPI_MOSI input hold time 1 2 ns Tod SPI_MISO clock to output delay 1 5 8 75 ns CL Output Load 5 10 pF Table 17 AC Characteristics SPI Slave Ultra High Speed Mode Fi...

Page 37: ...teristics USB Full Speed Mode 3 4 4 3 High Speed Mode Parameter Parameter Description Min Typ Max Unit Tr Rise Time 0 5 ns Tf Fall Time 0 5 ns Jitter Jitter 0 1 ns Table 20 AC Characteristics USB High Speed Mode 3 4 5 UART Parameter Parameter Description Min Typ Max Unit Tuart CLK 0 20 MHz Tod Output delay 0 10 ns Ts Input setup time 0 5 ns CL Output load 5 25 pF Table 21 AC Characteristics UART 3...

Page 38: ...igure 12 Interface Timing Diagram for I2C Fast Speed Mode 3 4 6 2 High Speed Mode Parameter Parameter Description Min Typ Max Unit Ti2c SCL 0 4 3 4 MHz Tlow clock low period 160 ns Thigh clock high period 60 ns Tsstart start condition setup time 160 ns Thstart start condition hold time 160 ns Ts data setup time 10 ns Th data hold time 0 70 ns Tsstop stop condition setup time 160 ns CL Output Load ...

Page 39: ...10 ns Th i2s_din i2s_ws hold time 0 ns Tod i2s_dout output delay 0 12 ns CL i2s_dout output load 5 10 pF Table 24 AC Characteristics I2S PCM Master Mode Figure 14 Interface Timing Diagram for I2S Master Mode 3 4 7 2 Slave Mode Negedge driving and posedge sampling for I2S Posedge driving and negedge sampling for PCM Parameter Parameter Description Min Typ Max Unit Ti2s i2s_clk 0 25 MHz Ts i2s_din i...

Page 40: ...itions Min Typ Max Unit Trf Rise time Pin configured as output SLEW 1 fast mode 1 0 2 5 ns Tff Fall time Pin configured as output SLEW 1 fast mode 0 9 2 5 ns Trs Rise time Pin configured as output SLEW 0 standard mode 1 9 4 3 ns Tfs Fall time Pin configured as output SLEW 0 standard mode 1 9 4 0 ns Tr Rise time Pin configured as input 0 3 1 3 ns Tf Fall time Pin configured as input 0 2 1 2 ns Tabl...

Page 41: ...ce across channels Parameter Condition Notes Min Typ Max Units Transmit Power for 20 MHz Bandwidth compliant with IEEE mask and EVM DSSS 1 Mbps EVM 9 dB 17 5 dBm DSSS 2 Mbps EVM 9 dB 17 5 dBm CCK 5 5 Mbps EVM 9 dB 17 5 dBm CCK 11 Mbps EVM 9 dB 15 5 dBm OFDM 6 Mbps EVM 5 dB 16 5 dBm OFDM 9 Mbps EVM 8 dB 15 5 dBm OFDM 12 Mbps EVM 10 dB 15 5 dBm OFDM 18 Mbps EVM 13 dB 16 dBm OFDM 24 Mbps EVM 16 dB 15...

Page 42: ...2496 2530 MHz LTE Band 41 102 dBm Hz 2530 2560 MHz LTE Band 41 113 dBm Hz 2570 2690 MHz LTE Band 41 128 dBm Hz 5000 5900 MHz WLAN 5G 148 dBm Hz Harmonic Emissions 1 Mbps Maximum Power 4 8 5 0 GHz 2nd Harmonic 40 dBm MHz 7 2 7 5 GHz 3rd Harmonic 43 dBm MHz Table 27 WLAN 2 4 GHz Transmitter Characteristics 3 3V 1 There is a variation of up to 2 dB in power across parts and channels 2 To meet FCC emi...

Page 43: ... Typ Max Units Sensitivity for 20 MHz Bandwidth 1 1 Mbps DSSS 96 dBm 2 Mbps DSSS 90 dBm 5 5 Mbps CCK 89 dBm 11 Mbps CCK 86 5 dBm 6 Mbps OFDM 90 dBm 9 Mbps OFDM 89 dBm 12 Mbps OFDM 89 dBm 18 Mbps OFDM 87 dBm 24 Mbps OFDM 84 dBm 36 Mbps OFDM 80 dBm 48 Mbps OFDM 75 5 dBm 54 Mbps OFDM 74 dBm MCS0 Mixed Mode 89 5 dBm MCS1 Mixed Mode 87 dBm MCS2 Mixed Mode 84 dBm MCS3 Mixed Mode 82 dBm MCS4 Mixed Mode 7...

Page 44: ...DM 30 dB MCS0 Mixed Mode 46 dB MCS7 Mixed Mode 28 dB Table 28 WLAN 2 4 GHz Receiver Characteristics on HP RF Chain 1 Receiver sensitivity may be degraded by up to 4 dB for channels 6 7 8 13 14 due to desensitization of the receiver by harmonics of the system clock 40 MHz 2 There may be a degradation of up to 2 dB across the operating temperature range of 40 C to 85 C 3 5 3 WLAN 2 4 GHz Receiver Ch...

Page 45: ...ng level for 3 dB RX Sensitivity Degradation Data rate 6Mbps OFDM Desired signal at 79dBm 776 794 MHz 8 dBm 824 849 MHz 8 dBm 880 915 MHz 10 dBm 1710 1785 MHz 16 dBm 1850 1910 MHz 14 dBm 1920 1980 MHz 20 dBm 2300 2400 MHz 55 dBm 2570 2620 MHz 24 dBm 2545 2575 MHz 23 dBm Return Loss 10 dB Adjacent Channel Interference 1 Mbps DSSS 40 dB 11 Mbps DSSS 36 dB 6 Mbps OFDM 42 dB 36 Mbps OFDM 30 dB MCS0 Mi...

Page 46: ...KDC 3 3 V Remaining supplies are at typical operating conditions Parameters are measured at the antenna port 1 For Bluetooth C I cases the desired signal power is 3 dB above standard defined sensitivity level Parameter Condition Notes Min Typ Max Units Transmit Power BR 12 dBm EDR 2Mbps 12 dBm EDR 3Mbps 11 dBm LE 1Mbps 17 dBm LE 2Mbps 17 dBm LR 500 Kbps 17 dBm LR 125 Kbps 17 dBm Power Control Step...

Page 47: ...dBm Hz 1570 1580 MHz GPS 160 dBm Hz 1592 1610 MHz GLONASS 160 2 dBm Hz 1710 1800 MHz DSC 1800 Uplink 115 dBm Hz 1805 1880 MHz GSM 1800 148 dBm Hz 1850 1910 MHz GSM 1900 148 dBm Hz 1910 1930 MHz TDSCDMA LTE 135 dBm Hz 1930 1990 MHz GSM1900 CDMAOne WCDMA 101 dBm Hz 2010 2075 MHz TDSCDMA 148 dBm Hz 2110 2170 MHz WCDMA 115 dBm Hz 2305 2370 MHz LTE Band 40 140 dBm Hz 2370 2400 MHz LTE Band 40 134 dBm H...

Page 48: ... 5 dBm LE 1Mbps 3 5 dBm LE 2Mbps 3 5 dBm LR 500 Kbps 3 5 dBm LR 125 kbps 3 5 dBm Adjacent Channel Power M N 2 BR 20 dBm LE 20 dBm LR 20 dBm Adjacent Channel Power M N 2 BR 40 dBm LE 30 dBm LR 30 dBm BR Modulation Characteristics DH1 25 25 kHz DH3 40 40 kHz DH5 40 40 kHz Drift Rate 20 20 kHz Δf1 Avg 140 175 kHz Δf2 Max 115 kHz BLE Modulation Characteristics Δf1 Avg 225 275 kHz Δf2 Max 185 kHz Δf2 A...

Page 49: ...dBm LE 1 Mbps 37 bytes PER 30 8 92 dBm LE 2 Mbps 37 bytes PER 30 8 90 dBm LR 500 Kbps 37 bytes PER 30 8 99 dBm LR 125 Kbps 37 bytes PER 30 8 103 dBm Maximum Input Level BR EDR2 EDR3 BER 0 1 15 dBm LE 1Mbps 2Mbps PER 30 8 1 dBm LR 500kps 125kbps PER 30 8 10 dBm C I Performance BR co channel BER 0 1 9 dB BR adjacent 1 1 MHz BER 0 1 2 dB BR adjacent 2 2 MHz BER 0 1 19 dB BR adjacent 3 MHz BER 0 1 19 ...

Page 50: ...jacent 1 MHz PER 30 8 2 dB LE 1Mbps adjacent 2 MHz PER 30 8 23 dB LE 1Mbps adjacent 2 MHz PER 30 8 24 dB LE 1Mbps adjacent 3 MHz PER 30 8 21 dB LE 1Mbps adjacent 3 MHz PER 30 8 27 dB LE 1Mbps adjacent 4 MHz PER 30 8 35 dB LE 1Mbps Image channel PER 30 8 24 dB LE 1Mbps 1MHz adjacent to Image channel PER 30 8 34 dB LE 1Mbps 1MHz adjacent to Image channel PER 30 8 21 dB LE 2Mbps co channel PER 30 8 1...

Page 51: ...clock 40MHz 3 There may be a degradation of up to 2 dB across the operating temperature range of 40 C to 85 C 3 5 7 Bluetooth Receiver Characteristics on Low Power LP RF Chain TA 25 C Parameters are measured at the antenna port and applicable to PA2G_AVDD VINBCKDC 3 3V Parameter Condition Notes Min Typ Max Units Sensitivity Dirty TX off 1 2 BR 1 Mbps 339 bytes DH5 Packet BER 0 1 86 dBm EDR2 2 Mbps...

Page 52: ...mage channel BER 0 1 22 dB LE 1Mbps co channel PER 30 8 10 dB LE 1Mbps adjacent 1 MHz PER 30 8 1 dB LE 1Mbps adjacent 1 MHz PER 30 8 1 dB LE 1Mbps adjacent 2 MHz PER 30 8 23 dB LE 1Mbps adjacent 2 MHz PER 30 8 23 dB LE 1Mbps adjacent 3 MHz PER 30 8 22 dB LE 1Mbps adjacent 3 MHz PER 30 8 27 dB LE 1Mbps adjacent 4 MHz PER 30 8 33 dB LE 1Mbps Image channel PER 30 8 27 dB LE 1Mbps 1MHz adjacent to Ima...

Page 53: ...s degraded by up to 8 dB for channels 19 29 30 39 due to the desensitization of the receiver from harmonics of the system clock 40MHz 3 There may be a degradation of up to 2 dB across the operating temperature range of 40 C to 85 C 3 5 8 WLAN 5GHz Transmitter Characteristics TA 25 C Parameters are measured at antenna port on 3 channels and 3 frequency bands 1 Parameter Condition Notes Min Typ Max ...

Page 54: ...IEEE mask and EVM Frequency Band 5500 5600 MHz OFDM 6 Mbps EVM 5 dB 11 dBm OFDM 9 Mbps EVM 8 dB 11 5 dBm OFDM 12 Mbps EVM 10 dB 11 5 dBm OFDM 18 Mbps EVM 13 dB 11 5 dBm OFDM 24 Mbps EVM 16 dB 11 5 dBm OFDM 36 Mbps EVM 19 dB 8 5 dBm OFDM 48 Mbps EVM 22 dB 7 dBm OFDM 54 Mbps EVM 25 dB 6 5 dBm MCS0 Mixed Mode EVM 5 dB 11 5 dBm MCS1 Mixed Mode EVM 10 dB 11 5 dBm MCS2 Mixed Mode EVM 13 dB 11 5 dBm MCS3...

Page 55: ... EVM 25 dB 3 5 dBm MCS0 Mixed Mode EVM 5 dB 9 dBm MCS1 Mixed Mode EVM 10 dB 9 5 dBm MCS2 Mixed Mode EVM 13 dB 9 5 dBm MCS3 Mixed Mode EVM 16 dB 9 5 dBm MCS4 Mixed Mode EVM 19 dB 7 dBm HT MCS5 EVM 22 dB 5 5 dBm HT MCS6 EVM 25 dB see note section 3 5 dBm HT MCS7 EVM 27 dB see note section 1 dBm Transmitter Emissions 6 Mbps Maximum Power 776 794 MHz CDMA2000 159 dBm Hz 869 960 MHz CDMAOne GSM850 159 ...

Page 56: ... to 85 C 3 There may be a reduction in EVM of up to 1 dB in MCS6 data rate and 2 dB in MCS7 data rate 4 IEEE spectral mask limits may be crossed in lower data rates in some channels and if required power may be backed off by 1 2 dB 3 5 9 WLAN 5GHz Receiver Characteristics TA 25 C Parameters are measured at antenna port on 3 channels and 3 frequency bands 1 Parameter Condition Notes Min Typ Max Uni...

Page 57: ... Mode 83 dBm MCS2 Mixed Mode 81 dBm MCS3 Mixed Mode 78 dBm MCS4 Mixed Mode 74 5 dBm MCS5 Mixed Mode 70 dBm MCS6 Mixed Mode 67 dBm MCS7 Mixed Mode 67 5 dBm Sensitivity for 20 MHz Bandwidth 1 Frequency Band 5725 5825 MHz 6 Mbps OFDM 85 dBm 9 Mbps OFDM 84 dBm 12 Mbps OFDM 83 5 dBm 18 Mbps OFDM 81 dBm 24 Mbps OFDM 78 dBm 36 Mbps OFDM 74 5 dBm 48 Mbps OFDM 70 5 dBm 54 Mbps OFDM 69 dBm MCS0 Mixed Mode 8...

Page 58: ...dBm 880 915 MHz 2 dBm 1710 1785 MHz 2 dBm 1850 1910 MHz 3 dBm 1920 1980 MHz 3 dBm 2500 2570 MHz 6 dBm 2300 2400 MHz 8 dBm 2570 2620 MHz 6 dBm 2545 2575 MHz 5 dBm Return Loss 10 4 5 dB Adjacent Channel Interference 6 Mbps OFDM 16 19 dB 9 Mbps OFDM 15 18 dB 12 Mbps OFDM 13 19 dB 18 Mbps OFDM 11 18 dB 24 Mbps OFDM 8 17 dB 36 Mbps OFDM 4 20 dB 48 Mbps OFDM 0 14 dB 54 Mbps OFDM 1 15 dB MCS7 Mixed Mode ...

Page 59: ...g 6 Mbps RX Active HP Chain 41 mA IEEE 802 11g 72 Mbps RX Active HP Chain 42 mA 11 Mbps TX Active Tx Power Maximum 18dBm Tx Power 8dBm 270 130 mA mA IEEE 802 11g 6 Mbps TX Active Tx Power Maximum 18dBm Tx Power 8dBm 285 130 mA mA IEEE 802 11g 54 Mbps TX Active Tx Power Maximum 15dBm Tx Power 8dBm 200 130 mA mA IEEE 802 11g 72 Mbps TX Active Tx Power Maximum 12dBm Tx Power 8dBm 180 130 mA mA Deep S...

Page 60: ...70 uA Standby Associated DTIM 10 5 GHz Band 265 uA 3 6 1 3 Bluetooth BR and EDR Parameter Description Value Units TX Active Current 1 Mbps BR LP chain Tx Power 2 dBm HP chain Tx Power Maximum 12 dBm 9 9 130 mA mA RX Active Current 1 Mbps BR LP chain HP chain 10 2 26 7 mA mA TX Active Current 2 Mbps EDR HP chain Tx Power Maximum 12 dBm 130 mA RX Active Current 2 Mbps EDR LP chain HP chain 10 2 26 7...

Page 61: ...d 13 1 uA Advertising Unconnectable Advertising on all 3 channels Advertising Interval 1 28s Tx Power 2 dBm LP chain 45 uA Advertising Connectable Advertising on all 3 channels Advertising Interval 1 28s Tx Power 2 dBm LP chain 60 uA Connected Connection Interval 1 28s No Data Tx Power 2 dBm LP chain 44 uA Connected Connection Interval 200ms No Data Tx Power 0 dBm LP chain 144 uA ...

Page 62: ...nt to 1x1 IEEE 802 11 a b g n with dual band 2 4 and 5 GHz support Transmit power up to 18 dBm in 2 GHz and 13 5 dBm in 5 GHz Receive sensitivity as low as 96 dBm in 2 GHz and 89 dBm in 5 GHz Data Rates 802 11b Up to 11 Mbps 802 11g a Up to 54 Mbps 802 11n MCS0 to MCS7 Operating Frequency Range 2412 MHz 2484 MHz 4 9 GHz 5 975 GHz 4 2 1 1 MAC Conforms to IEEE 802 11b g n j standards for MAC Dynamic...

Page 63: ...required QOS Support for security using ECDH hardware accelerator 4 2 2 1 2 Link Controller Encodes and decodes header of BT packets Manages flow control acknowledgment retransmission requests etc Stores the last packet status for all logical transports Chooses between SCO ACL buffers depending on the control information coming from BBP resource manager Indicates the success status of packet trans...

Page 64: ...to respective host controllers like SDIO SPI UART USB and USB CDC SDIO SPI host interface is detected through the hardware packet exchanges UART host interface is detected through the software based on the received packets on the UART interface USB Device mode interface is detected through the hardware based on VBUS signal level The host interface detection between USB USB CDC will be taken care b...

Page 65: ... 5 4 2 6 2 Embedded Mode WiSeConnect Available host interface UART SPI and USB CDC Support for Embedded Client mode Access Point mode Up to 8 clients Concurrent Client and Access Point mode and Enterprise Security Supports advanced security features WPA WPA2 Personal and Enterprise Integrated TCP IP stack HTTP HTTPS SSL TLS MQTT Bluetooth inbuilt stack support for L2CAP RFCOMM SDP SPP GAP Bluetoot...

Page 66: ...n Description Supply Voltage V Min Max VOUTLDOSOC 1 05 1 2 VOUTLDO1P8 1 75 2 0 VOUTBCKDC 1 25 1 55 VOUTLDOAFE 1 0 1 21 UULP_VOUTSCDC 1 02 1 2 UULP_VOUTSCDC_RETN 0 715 1 2 Table 36 Min and Max specifications of various output voltages The output voltages from the IC module will be reflected as per specifications only after the firmware is loaded 4 2 9 Low Power Modes It supports Ultra low power con...

Page 67: ...and the clock is gated immediately after the completion of the operation to reduce power consumption GPIO based wakeup Wakeup can be initiated through a GPIO pin Timeout wakeup Exit sleep state after the programmed timeout value 4 2 10 Memory 4 2 10 1 On chip Memory The ThreadArch processor has the following memory On chip SRAM for the wireless stack 512Kbytes of ROM which holds the Secure primary...

Page 68: ...t points so designers could use the faster interface for programming the firmware as needed 3 If using SPI as host interface then firmware programming or update can be done through the host MCU or if designer prefers to program standalone at manufacturing then it is recommended to have test points on the SPI signals 4 If SDIO SPI UART interface is not used then their respective IO domains must sti...

Page 69: ...GND N13 GND N11 GND N2 GND N1 GND M14 GND M13 GND F2 NC1 A1 NC10 G2 NC11 G6 NC12 K13 NC13 K14 NC14 L8 NC15 L14 NC16 M7 NC17 M8 NC18 N3 NC19 N4 NC2 A2 NC20 N6 NC21 N9 NC22 N10 NC23 C3 NC24 G7 NC25 C8 NC26 C7 NC3 A13 NC4 C1 NC5 D2 NC6 E1 NC7 E3 NC8 E4 NC9 G1 C11 0 1uF TP4 R2 0E J1 Antenna U FL 1 2 3 C9 1uF L1 1uH J2 Antenna U FL 1 2 3 U1A RS9116X XB00 CX0 VINBCKDC B4 ULP_IO_VDD B6 VOUTBCKDC C5 VINLD...

Page 70: ... Active high or Active low mode ensure that during the power up of the device the Interrupt is disabled in the Host processor before deasserting the reset After deasserting the reset the Interrupt needs to be enabled only after the SPI initialization is done and the Interrupt mode is programmed to either Active high or Active low mode as required b The Host processor needs to be disable the interr...

Page 71: ...U1 Wireless Single Dual Band Module Silicon Labs RS9116W DB00 CC0 B2A RS9116N DB00 CC0 B00 9 2 Z1 Z4 8 2pF CER CHP 8 2P 0 25P C0G 0201 25V 0201 Murata GRM0335C1E8R2CD01D 10 4 Z2 Z3 Z5 Z6 Optional Capacitors for Antenna Matching 0201 Table 37 Bill of Materials with SDIO SPI UART Host Interface 5 2 USB USB CDC 5 2 1 Schematics The diagram below shows the typical schematic with USB USB CDC Host Inter...

Page 72: ...2 NC1 A1 NC10 G2 NC11 G6 NC12 K13 NC13 K14 NC14 L8 NC15 L14 NC16 M7 NC17 M8 NC18 N3 NC19 N4 NC2 A2 NC20 N6 NC21 N9 NC22 N10 NC23 C3 NC24 G7 NC25 C8 NC26 C7 NC3 A13 NC4 C1 NC5 D2 NC6 E1 NC7 E3 NC8 E4 NC9 G1 Z3 TBD R2 0E C12 1uF C13 0 1uF L1 1uH TP1 C1 10uF J2 Antenna U FL 1 2 3 C10 1uF C6 0 1uF C14 0 1uF Z4 8 2pF C7 10uF C16 0 1uF TP8 TP6 TP2 C3 0 1uF C5 0 1uF U1B RS9116X XB00 CX0 GPIO_6 E14 GPIO_7...

Page 73: ...2 C1 C7 10uF CAP CER 10UF 10V X5R 0805 0805 Murata GRM21BR61A106KE19L 2 5 C2 C8 C9 C10 C12 1uF CAP CER 1UF 10V 10 X5R 0402 0402 Murata GRM155R61A105KE15D 3 9 C3 C4 C5 C6 C 11 C13 C14 C1 6 C17 0 1uF CAP CER 0 1UF 10V X5R 0402 0402 Murata GRM155R61A104KA01D 4 2 J1 J2 Antenna U FL 5 1 L1 1uH FIXED IND 1UH 1 0A 95 MOHM SMD 0805 Murata DFE201210U 1R0M P2 6 1 R1 4 7K RES SMD 4 7K OHM 1 1 16W 0402 0402 Y...

Page 74: ...ctor switching node output capacitors input capacitors This helps keep high current paths as short as possible Keeping high current paths shorter and wider would help decrease trace inductance resistance This would significantly help increase the efficiency in high current applications This reduced loop area would also help in reducing the radiated EMI that may affect nearby components a VINBCKDC ...

Page 75: ...acing for Low Speed and High Speed Signals Around USB_DP USB_DN 10 It is recommended that the total trace length of the signals between the RS9116 module and the USB connector be less than 450mm 11 If the USB high speed signals are routed on the Top layer best results will be achieved if Layer2 is a Ground plane Furthermore there must be only one ground plane under high speed signals in order to a...

Page 76: ... 0 10 76 Page 14 Ensure all power supply traces widths are sufficient enough to carry corresponding currents 15 Add GND copper pour underneath IC Module in all layers for better thermal dissipation Note When using Chip Antenna from vendors the Chip Antenna layout guidelines provided by the vendor need to be used ...

Page 77: ...abs com Building a more connected world Rev 1 0 10 77 Page 6 RS9116 CC0 Module Package Description 6 1 Dimensions Parameter Value LxWxH Units Module Dimensions 9 1 x 9 8 x 1 6 mm Tolerance 0 2 mm Table 39 Module Dimensions 6 2 Package Outline Figure 21 Package Outline ...

Page 78: ...15 2 1 H4 2 45 0 7 L10 1 75 2 8 A11 2 45 4 2 D13 3 85 2 1 H5 1 75 0 7 L11 2 45 2 8 A12 3 15 4 2 D14 4 55 2 1 H6 1 05 0 7 L12 3 15 2 8 A13 3 85 4 2 E1 4 55 1 4 H7 0 35 0 7 L13 3 85 2 8 A14 4 55 4 2 E2 3 85 1 4 H8 0 35 0 7 L14 4 55 2 8 B1 4 55 3 5 E3 3 15 1 4 H9 1 05 0 7 M1 4 55 3 5 B2 3 85 3 5 E4 2 45 1 4 H10 1 75 0 7 M2 3 85 3 5 B3 3 15 3 5 E5 1 75 1 4 H11 2 45 0 7 M3 3 15 3 5 B4 2 45 3 5 E6 1 05 ...

Page 79: ...1 75 4 2 C5 1 75 2 8 F10 1 75 0 7 J14 4 55 1 4 N6 1 05 4 2 C6 1 05 2 8 F11 2 45 0 7 K1 4 55 2 1 N7 0 35 4 2 C7 0 35 2 8 F12 3 15 0 7 K2 3 85 2 1 N8 0 35 4 2 C8 0 35 2 8 F13 3 85 0 7 K3 3 15 2 1 N9 1 05 4 2 C9 1 05 2 8 F14 4 55 0 7 K4 2 45 2 1 N10 1 75 4 2 C10 1 75 2 8 G1 4 55 0 K5 1 75 2 1 N11 2 45 4 2 C11 2 45 2 8 G2 3 85 0 K6 1 05 2 1 N12 3 15 4 2 C12 3 15 2 8 G3 3 15 0 K8 0 35 2 1 N13 3 85 4 2 ...

Page 80: ... 10 80 Page 6 4 PCB Landing Pattern Figure 22 PCB Landing Pattern 6 4 1 Packing Information of Modules with Package Codes CC0 The modules are packaged and shipped in Trays Each tray for the CC0 package can accommodate 168 modules The mechanical details of the tray for the CC0 package are given in the figure below ...

Page 81: ...RS9116 CC0 Connectivity Module Datasheet v1 0 10 December 2021 silabs com Building a more connected world Rev 1 0 10 81 Page Figure 23 Packing Information of Modules with Package Codes CC0 ...

Page 82: ...e incorporated into the product and no change in the module circuitry Without these certifications an end product cannot be marketed in the relevant regions RF Testing Software is provided for any end product certification requirements 7 2 1 Federal Communication Commission Statement Any changes or modifications not expressly approved by the party responsible for compliance could void your authori...

Page 83: ...t utilize avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps This device complies with Industry Canada license exempt RSSs Operation is subject to the following two conditions 1 This device may not cause interference and 2 This device must accept any interference including interference that may cause undesired operation of the device Le present appareil est conforme...

Page 84: ...reil ne peut pas émettre dans la bande 5600 5650 MHz au Canada 7 2 3 CE The modules are in conformity with the essential requirements and other relevant requirements of the R TTE Directive 1999 5 EC for M7DB6 and RE Directive 2014 53 EU for M7DB The product is conformity with the following standards and or normative documents EMC EN 301 489 1 V2 2 3 2019 11 EN 301 489 17 V3 2 4 2020 09 Radiated em...

Page 85: ... 5153 Dipole Antenna 3 8 dBi Bent 3 3 dBi Straight 5 5 dBi Bent 4 9 dBi Straight FCC IC CE TELEC Smarteq 4211613980 PIFA 0 dBi 2 0 dBi FCC IC CE TELEC Inside WLAN PRO IS 299 Dipole 2 5 dBi 1 6 dBi FCC IC CE TELEC Joinsoon Electronics Mfg Co Ltd MARS 31A8 WiFi Antenna PIFA 2 0 dBi 2 0 dBi FCC IC CE TELEC Table 42 Qualified Antenna List for M7DB Note If certification with PCB Trace Antenna is requir...

Page 86: ... TTTTTT Trace or manufacturing code The first letter is the device revision Compliance Marks FCC Compliance Mark CE Compliance Mark TELEC Compliance Mark 7 3 Module Package Package Code Package Type Pins Dimensions mm Frequency Band Integrated Antenna CC0 SIP LGA 173 9 1 x 9 8 x 1 6 Dual Band 2 4 GHz 5 GHz No Table 43 CC0 Module Package 7 4 Ordering Information Part Number Wireless Hosted Connecti...

Page 87: ...eloping products and applications using RS9116 These documents are available in RS9116 Document Library on the Silicon Labs website The documents include information related to Software releases Evaluation Kits User Guides Programming Reference Manuals Application Notes and others For further assistance you can contact Silicon Labs Technical Support here 8 1 Resource Location RS9116 Document Libra...

Page 88: ...ations section Added external control for POC_IN in Specifications Added host detection details and updated network processor memory details in Detailed description Renamed LP_WAKEUP to LP_WAKEUP_IN and changed its description in Pinout section Removed PLL_AVDD from Recommended Operating conditions section Corrected the initial state of SDIO_D3 to pullup and SDIO_D2 to HighZ 5 1 0 4 November 2019 ...

Page 89: ...to include Silicon revision and firmware version Updated schematics to include the new nomenclature SoC Ordering information updated with new OPNs Device Nomenclature diagram updated 9 1 0 8 December 2020 Updated 2 4 GHz TX numbers using new gain tables Band separation and updated values provided for TX and RX for 5 GHz RF characteristics Updated Feature Set for Embedded Mode Included DTIM 1 3 val...

Page 90: ...iations for RF Tx and Rx readings Added caveats to RF Characteristics Updated RF Specification section to include numbers at 3 3 V only Updated 2 4 GHz Transmitter characteristics at 11 Mbps and 6 Mbps to reflect corrected values based on latest ATE power index table Updated Note for IEEE spectral mask effects Added mention of AN1337 application note for certification details Included output volta...

Page 91: ...ematics regarding power supply to IO domain when any interface signal is not used Updated UULP_VBATT power pins to reference to the correct minimum voltage under Power Management Output Voltage Specs updated for VOUTLDOAFE and VOUTSCDC Updated note under RF Characteristics to state that the 2 dBm variation is across parts and channels and not channels alone Corrected Operating Voltage range and Te...

Page 92: ...RS9116 CC0 Connectivity Module Datasheet v1 0 10 December 2021 silabs com Building a more connected world Rev 1 0 10 92 Page ...

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